FPGA Implementations of Layered MinSum LDPC Decoders Using RCQ Message Passing. - Caleb Terrill; Linfang Wang; Sean Chen; Chester Hulse; Calvin Kuo; Richard D. Wesel; Dariush Divsalar (GLOBECOM, 2021)

BEANNA: A Binary-Enabled Architecture for Neural Network Acceleration. - Caleb Terrill; Fred Chu (CoRR, 2021)

Reconstruction-Computation-Quantization (RCQ): A Paradigm for Low Bit Width LDPC Decoding. - Linfang Wang; Caleb Terrill; Maximilian Stark; Zongwang Li; Sean Chen; Chester Hulse; Calvin Kuo; Richard D. Wesel; Gerhard Bauch 001; Rekha Pitchumani (IEEE Trans. Commun., 2022)

Efficiently Synthesizing Lowest Cost Rewrite Rules for Instruction Selection. - Ross Daly; Caleb Donovick; Caleb Terrill; Jackson Melchert; Priyanka Raina; Clark W. Barrett; Pat Hanrahan (FMCAD, 2024)

If Layering is useful, why not Sublayering? - Rathin Singha; Rishabh R. Iyer; Charles Liu; Caleb Terrill; Todd D. Millstein; Scott Shenker; George Varghese (HotNets, 2024)

LDPC Decoding With Degree-Specific Neural Message Weights and RCQ Decoding. - Linfang Wang; Caleb Terrill; Dariush Divsalar; Richard D. Wesel (IEEE Trans. Commun., 2024)