Efficient emulation of quantum circuits on classical hardware. - Calebe Conceição; Ricardo Reis 001 (LASCAS, 2015)

Reducing the number of transistors with gate clustering. - Calebe Conceição; Gracieli Posser; Ricardo Reis 001 (LASCAS, 2016)

A cell clustering technique to reduce transistor count. - Calebe Conceição; Gisell Moura; Filipe Pisoni; Ricardo Reis 001 (ICECS, 2017)

Exploring area and total wirelength using a cell merging technique. - Kevin A. Cáceres Albinagorta; Calebe Conceição; Carlos Silva Cárdenas; Ricardo A. L. Reis (VLSI-SoC, 2019)

Netlist Optimization by Gate Merging. - Calebe Micael de Oliveira Conceição; Ricardo Augusto da Luz Reis (VLSI-SoC, 2019)

Transistor Count Reduction by Gate Merging. - Calebe Micael de Oliveira Conceição; Ricardo Augusto da Luz Reis (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Security Issues in the Design of Chips for IoT. - Calebe Micael de Oliveira Conceição; Ricardo Augusto da Luz Reis (WF-IoT, 2020)

Minimizing transistor count in transistor networks - Calebe Micael de Oliveira Conceição (2020)