A collaborative environment for independent verification and validation of software. - Raghu Karinthi; Kankanahalli Srinivas; Sumitra Reddy; Ramana Reddy; Calin Cascaval; Walter Jackson; Srinivasan Venkatraman; Honglan Zheng (WETICE, 1994)

Web - A Technology to Make Information Available on the Web. - George Almási 001; Anca Suvaiala; Ion Muslea; Calin Cascaval; Tad Davis; Vasudevan Jagannathan (WETICE, 1995)

MATmarks: A Shared Memory Environment for MATLAB Programming. - George Almási 001; Calin Cascaval; David A. Padua (HPDC, 1999)

Compile-Time Based Performance Prediction. - Calin Cascaval; Luiz De Rose; David A. Padua; Daniel A. Reed (LCPC, 1999)

Compile-Time Performance Prediction of Scientific Programs - Calin Cascaval (2000)

Demonstrating the scalability of a molecular dynamics application on a Petaflop computer. - George S. Almási; Calin Cascaval; José G. Castaños; Monty Denneau; Wilm E. Donath; Maria Eleftheriou; Mark Giampapa; C. T. Howard Ho; Derek Lieber; José E. Moreira; Dennis M. Newns; Marc Snir; et al. (ICS, 2001)

Blue Gene: A vision for protein science using a petaflop supercomputer. - Frances E. Allen; George S. Almási; Wanda Andreoni; Daniel K. Beece; Bruce J. Berne; Arthur A. Bright; José R. Brunheroto; Calin Cascaval; José G. Castaños; Paul Coteus; Paul Crumley; Alessandro Curioni; et al. (IBM Syst. J., 2001)

Blue Gene/L, a System-On-A-Chip. - George S. Almási; Daniel K. Beece; Ralph Bellofatto; Gyan Bhanot; Randy Bickford; Matthias A. Blumrich; Arthur A. Bright; José R. Brunheroto; Calin Cascaval; José G. Castaños; Luis Ceze; Paul Coteus; et al. (CLUSTER, 2002)

Evaluation of a Multithreaded Architecture for Cellular Computing. - Calin Cascaval; José G. Castaños; Luis Ceze; Monty Denneau; Manish Gupta 002; Derek Lieber; José E. Moreira; Karin Strauss; Henry S. Warren Jr. (HPCA, 2002)

Calculating stack distances efficiently. - George Almási 001; Calin Cascaval; David A. Padua (MSP/ISMM, 2002)

An overview of the BlueGene/L Supercomputer. - Narasimha R. Adiga; George Almási 001; George S. Almási; Yariv Aridor; Rajkishore Barik; Daniel K. Beece; Ralph Bellofatto; Gyan Bhanot; Randy Bickford; Matthias A. Blumrich; Arthur A. Bright; José R. Brunheroto; et al. (SC, 2002)

Demonstrating the Scalability of a Molecular Dynamics Application on a Petaflops Computer. - George S. Almási; Calin Cascaval; José G. Castaños; Monty Denneau; Wilm E. Donath; Maria Eleftheriou; Mark Giampapa; C. T. Howard Ho; Derek Lieber; José E. Moreira; Dennis M. Newns; Marc Snir; et al. (Int. J. Parallel Program., 2002)

Characterizing and Predicting Program Behavior and its Variability. - Evelyn Duesterwald; Calin Cascaval; Sandhya Dwarkadas (IEEE PACT, 2003)

An Overview of the Blue Gene/L System Software Organization. - George Almási 001; Ralph Bellofatto; José R. Brunheroto; Calin Cascaval; José G. Castaños; Luis Ceze; Paul Crumley; C. Christopher Erway; Joseph Gagliano; Derek Lieber; Xavier Martorell; José E. Moreira; et al. (Euro-Par, 2003)

Estimating cache misses and locality using stack distances. - Calin Cascaval; David A. Padua (ICS, 2003)

System Management in the BlueGene/L Supercomputer. - George S. Almási; Leonardo R. Bachega; Ralph Bellofatto; José R. Brunheroto; Calin Cascaval; José G. Castaños; Paul Crumley; C. Christopher Erway; Joseph Gagliano; Derek Lieber; Pedro Mindlin; José E. Moreira; et al. (IPDPS, 2003)

Evaluation of OpenMP for the Cyclops Multithreaded Architecture. - George Almási 001; Eduard Ayguadé; Calin Cascaval; José G. Castaños; Jesús Labarta; Francisco Martínez; Xavier Martorell; José E. Moreira (WOMPAT, 2003)

An Overview Of The Bluegene/L System Software Organization. - George Almási 001; Ralph Bellofatto; José R. Brunheroto; Calin Cascaval; José G. Castaños; Paul Crumley; C. Christopher Erway; Derek Lieber; Xavier Martorell; José E. Moreira; Ramendra K. Sahoo; Alda Sanomiya; et al. (Parallel Process. Lett., 2003)

Dissecting Cyclops: a detailed analysis of a multithreaded architecture. - George Almási 001; Calin Cascaval; José G. Castaños; Monty Denneau; Derek Lieber; José E. Moreira; Henry S. Warren Jr. (SIGARCH Comput. Archit. News, 2003)

Multiple Page Size Modeling and Optimization. - Calin Cascaval; Evelyn Duesterwald; Peter F. Sweeney; Robert W. Wisniewski (IEEE PACT, 2005)

Optimizing NANOS OpenMP for the IBM Cyclops Multithreaded Architecture. - David Ródenas; Xavier Martorell; Eduard Ayguadé; Jesús Labarta; George Almási 001; Calin Cascaval; José G. Castaños; José E. Moreira (IPDPS, 2005)

Bulk Disambiguation of Speculative Threads in Multiprocessors. - Luis Ceze; James Tuck 001; Josep Torrellas; Calin Cascaval (ISCA, 2006)

A Characterization of Shared Data Access Patterns in UPC Programs. - Christopher Barton; Calin Cascaval; José Nelson Amaral (LCPC, 2006)

Shared memory programming for large scale machines. - Christopher Barton; Calin Cascaval; George Almási 001; Yili Zheng; Montse Farreras; Siddhartha Chatterjee; José Nelson Amaral (PLDI, 2006)

Performance and environment monitoring for continuous program optimization. - Calin Cascaval; Evelyn Duesterwald; Peter F. Sweeney; Robert W. Wisniewski (IBM J. Res. Dev., 2006)

Exploiting multilevel parallelism using OpenMP on a massive multithreaded architecture. - David Ródenas; Xavier Martorell; Eduard Ayguadé; Jesús Labarta; George Almási 001; Calin Cascaval; José G. Castaños; José E. Moreira (J. Embed. Comput., 2006)

Multidimensional Blocking in UPC. - Christopher Barton; Calin Cascaval; George Almási 001; Rahul Garg 001; José Nelson Amaral; Montse Farreras (LCPC, 2007)

Implicit parallelism with ordered transactions. - Christoph von Praun; Luis Ceze; Calin Cascaval (PPoPP, 2007)

Concurrency control with data coloring. - Luis Ceze; Christoph von Praun; Calin Cascaval; Pablo Montesinos; Josep Torrellas (MSPC, 2008)

Compiler-Driven Dependence Profiling to Guide Program Parallelization. - Peng Wu 001; Arun Kejariwal; Calin Cascaval (LCPC, 2008)

Performance without pain = productivity: data layout and collective communication in UPC. - Rajesh Nishtala; George Almási 001; Calin Cascaval (PPoPP, 2008)

Modeling optimistic concurrency using quantitative dependence analysis. - Christoph von Praun; Rajesh Bordawekar; Calin Cascaval (PPoPP, 2008)

Software Transactional Memory: Why Is It Only a Research Toy? - Calin Cascaval; Colin Blundell; Maged M. Michael; Harold W. Cain; Peng Wu 001; Stefanie Chiras; Siddhartha Chatterjee (ACM Queue, 2008)

Analytical Modeling of Pipeline Parallelism. - Angeles G. Navarro; Rafael Asenjo; Siham Tabik; Calin Cascaval (PACT, 2009)

Load balancing using work-stealing for pipeline parallelism in emerging applications. - Angeles G. Navarro; Rafael Asenjo; Siham Tabik; Calin Cascaval (ICS, 2009)

Scalable RDMA performance in PGAS languages. - Montse Farreras; George Almási 001; Calin Cascaval; Toni Cortes (IPDPS, 2009)

Lonestar: A suite of parallel irregular programs. - Milind Kulkarni 001; Martin Burtscher; Calin Cascaval; Keshav Pingali (ISPASS, 2009)

Parallelization spectroscopy: analysis of thread-level parallelism in hpc programs. - Arun Kejariwal; Calin Cascaval (PPoPP, 2009)

How much parallelism is there in irregular applications? - Milind Kulkarni 001; Martin Burtscher; Rajasekhar Inkulu; Keshav Pingali; Calin Cascaval (PPoPP, 2009)

The Bulk Multicore architecture for improved programmability. - Josep Torrellas; Luis Ceze; James Tuck 001; Calin Cascaval; Pablo Montesinos; Wonsun Ahn; Milos Prvulovic (Commun. ACM, 2009)

Compiler and runtime techniques for software transactional memory optimization. - Peng Wu 001; Maged M. Michael; Christoph von Praun; Takuya Nakaike; Rajesh Bordawekar; Harold W. Cain; Calin Cascaval; Siddhartha Chatterjee; Stefanie Chiras; Rui Hou; Mark F. Mergen; Xiaowei Shen; et al. (Concurr. Comput. Pract. Exp., 2009)

A taxonomy of accelerator architectures and their programming models. - Calin Cascaval; Siddhartha Chatterjee; Hubertus Franke; Kevin J. Gildea; Pratap Pattnaik (IBM J. Res. Dev., 2010)

A Case for Parallelizing Web Pages. - Haohui Mai; Shuo Tang; Samuel T. King; Calin Cascaval; Pablo Montesinos (HotPar, 2012)

Multidimensional dynamic behavior in mobile computing. - Mehrdad Reshadi; Calin Cascaval (IISWC, 2012)

Automatic discovery of performance and energy pitfalls in HTML and CSS. - Adrian Sampson; Calin Cascaval; Luis Ceze; Pablo Montesinos; Darío Suárez Gracia (IISWC, 2012)

Keynote talk: Parallel programming for mobile computing. - Calin Cascaval (PACT, 2013)

ZOOMM: a parallel web browser engine for multicore mobile devices. - Calin Cascaval; Seth Fowler; Pablo Montesinos-Ortego; Wayne Piekarski; Mehrdad Reshadi; Behnam Robatmili; Michael Weber 002; Vrajesh Bhavsar (PPoPP, 2013)

Guest Editorial: Computing Frontiers. - Calin Cascaval; Pedro Trancoso; Viktor K. Prasanna (Int. J. Parallel Program., 2013)

Deoptimization for dynamic language JITs on typed, stack-based virtual machines. - Madhukar N. Kedlaya; Behnam Robatmili; Calin Cascaval; Ben Hardekopf (VEE, 2014)

MuscalietJS: rethinking layered dynamic web runtimes. - Behnam Robatmili; Calin Cascaval; Mehrdad Reshadi; Madhukar N. Kedlaya; Seth Fowler; Vrajesh Bhavsar; Michael Weber 002; Ben Hardekopf (VEE, 2014)

Special Issue on Mobile Systems. - Calin Cascaval (IEEE Micro, 2015)

Concurrency in Mobile Browser Engines. - Calin Cascaval; Pablo Montesinos-Ortego; Behnam Robatmili; Darío Suárez Gracia (IEEE Pervasive Comput., 2015)

Abstract Representation of Shared Data for Heterogeneous Computing. - Tushar Kumar; Aravind Natarajan; Wenjia Ruan; Mario Badr; Darío Suárez Gracia; Calin Cascaval (LCPC, 2017)

p4v: practical verification for programmable data planes. - Jed Liu; William T. Hallahan; Cole Schlesinger; Milad Sharif; Jeongkeun Lee; Robert Soulé; Han Wang 009; Calin Cascaval; Nick McKeown; Nate Foster (SIGCOMM, 2018)

Modeling and Control of Google bittide Synchronization. - Sanjay Lall; Calin Cascaval; Martin Izzard; Tammo Spalink (CoRR, 2021)

Resistance Distance and Control Performance for Google bittide Synchronization. - Sanjay Lall; Calin Cascaval; Martin Izzard; Tammo Spalink (CoRR, 2021)

Modeling and Control of bittide Synchronization. - Sanjay Lall; Calin Cascaval; Martin Izzard; Tammo Spalink (ACC, 2022)

Resistance Distance and Control Performance for bittide Synchronization. - Sanjay Lall; Calin Cascaval; Martin Izzard; Tammo Spalink (ECC, 2022)

On Buffer Centering for Bittide Synchronization. - Sanjay Lall; Calin Cascaval; Martin Izzard; Tammo Spalink (CoDIT, 2023)

Logical Synchrony Networks: A Formal Model for Deterministic Distribution. - Logan Kenwright; Partha S. Roop; Nathan Allen; Sanjay Lall; Calin Cascaval; Tammo Spalink; Martin Izzard (IEEE Access, 2024)

Logical Synchrony and the Bittide Mechanism. - Sanjay Lall; Calin Cascaval; Martin Izzard; Tammo Spalink (IEEE Trans. Parallel Distributed Syst., 2024)

Timetide: A programming model for logically synchronous distributed systems. - Logan Kenwright; Partha S. Roop; Nathan Allen; Calin Cascaval; Avinash Malik (CoRR, 2025)