Performance and energy limits of a processor-integrated FFT accelerator. - Tung Thanh Hoang; Amirali Shambayati; Calvin Deutschbein; Henry Hoffmann; Andrew A. Chien (HPEC, 2014)

Preemptive Uniprocessor EDF Schedulability Analysis with Preemption Costs Considered. - Calvin Deutschbein; Sanjoy K. Baruah (RTSS, 2016)

End-to-End Automated Exploit Generation for Validating the Security of Processor Designs. - Rui Zhang 068; Calvin Deutschbein; Peng Huang 005; Cynthia Sturton (MICRO, 2018)

Mining Security Critical Linear Temporal Logic Specifications for Processors. - Calvin Deutschbein; Cynthia Sturton (MTV, 2018)

Multi-core cyclic executives for safety-critical systems. - Calvin Deutschbein; Tom Fleming; Alan Burns 001; Sanjoy K. Baruah (Sci. Comput. Program., 2019)

Evaluating Security Specification Mining for a CISC Architecture. - Calvin Deutschbein; Cynthia Sturton (HOST, 2020)

Isadora: Automated Information Flow Property Generation for Hardware Designs. - Calvin Deutschbein; Andres Meza 001; Francesco Restuccia 002; Ryan Kastner; Cynthia Sturton (ASHES@CCS, 2021)

A Methodology For Creating Information Flow Specifications of Hardware Designs. - Calvin Deutschbein; Andres Meza 001; Francesco Restuccia 002; Ryan Kastner; Cynthia Sturton (CoRR, 2021)

Mining Secure Behavior of Hardware Designs. - Calvin Deutschbein (CoRR, 2021)

End-to-End Automated Exploit Generation for Processor Security Validation. - Rui Zhang 068; Calvin Deutschbein; Peng Huang 005; Cynthia Sturton (IEEE Des. Test, 2021)

Mining Secure Behavior of Hardware Designs. - Calvin Deutschbein (2021)

Toward Hardware Security Property Generation at Scale. - Calvin Deutschbein; Andres Meza 001; Francesco Restuccia 002; Matthew Gregoire; Ryan Kastner; Cynthia Sturton (IEEE Secur. Priv., 2022)

Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance. - Sohrab Aftabjahani; Mark Tehranipoor; Farimah Farahmandi; Bulbul Ahmed; Ryan Kastner; Francesco Restuccia 002; Andres Meza 001; Kaki Ryan; Nicole Fern; Jasper Van Woudenberg; Rajesh Velegalati; Cees-Bart Breunesse; et al. (VTS, 2023)

Isadora: automated information-flow property generation for hardware security verification. - Calvin Deutschbein; Andres Meza 001; Francesco Restuccia 002; Ryan Kastner; Cynthia Sturton (J. Cryptogr. Eng., 2023)

"Test, Build, Deploy" - A CI/CD Framework for Open-Source Hardware Designs. - Calvin Deutschbein; Aristotle Stassinopoulos (CoRR, 2025)

"vcd2df" - Leveraging Data Science Insights for Hardware Security Research. - Calvin Deutschbein; Jimmy Ostler; Hriday Raj (CoRR, 2025)