Implementation of a Wavelet Transform Architecture for Image Processing. - Camille Diou; Lionel Torres; Michel Robert (VLSI, 1999)

A Wavelet Core for Video Processing. - Camille Diou; Lionel Torres; Michel Robert (ICIP, 2000)

An embedded core for the 2D wavelet transform. - Camille Diou; Lionel Torres; Michel Robert (ETFA (2), 2001)

The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems. - Gilles Sassatelli; Lionel Torres; Jérôme Galy; Gaston Cambon; Camille Diou (FPL, 2001)

Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications. - Gilles Sassatelli; Lionel Torres; Pascal Benoit; Thierry Gil; Camille Diou; Gaston Cambon; Jérôme Galy (DATE, 2002)

A multiprocessor architecture for fast packet processing. - Abbas Ramazani; Fabrice Monteiro; Camille Diou; Abbas Dandache (ICECS, 2005)

CodeRAKE: a new small-area scalable architecture for the multi-user/multi-code RAKE receiver. - Mazen Youssef; Camille Diou; Fabrice Monteiro; Abbas Dandache (ICECS, 2006)

A cost-effective parallel architecture for the CodeRAKE receiver. - Mazen Youssef; Fabrice Monteiro; Abbas Dandache; Camille Diou (ICECS, 2007)

Stack processor architecture and development methods suitable for dependable applications. - Mehdi Jallouli; Camille Diou; Fabrice Monteiro (ReCoSoC, 2007)

A HW/SW mixed mechanism to improve the dependability of a stack processor. - Mohsin Amin; Fabrice Monteiro; Camille Diou; Abbas Ramazani; Abbas Dandache (ICECS, 2009)

A fault tolerant journalized stack processor architecture. - Abbas Ramazani; Mohsin Amin; Fabrice Monteiro; Camille Diou; Abbas Dandache (IOLTS, 2009)

A Self-Checking HW Journal for a Fault Tolerant Processor Architecture. - Mohsin Amin; Camille Diou; Fabrice Monteiro; Abbas Ramazani; Abbas Dandache (ReCoSoC, 2010)

Behavioral modeling and C-VHDL co-simulation of Network on Chip on FPGA for Education. - Cédric Killian; Camel Tanougast; M. Monteiro; Camille Diou; Abbas Dandache; Slavisa Jovanovic (ReCoSoC, 2010)

A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture. - Mohsin Amin; Abbas Ramazani; Fabrice Monteiro; Camille Diou; Abbas Dandache (Int. J. Reconfigurable Comput., 2011)

A low-cost many-to-one WSN architecture based on UWB-IR and DWPT. - Mohamed Tabaa; Camille Diou (CoDIT, 2014)

LOS/NLOS Identification Based on Stable Distribution Feature Extraction and SVM Classifier for UWB On-Body Communications. - Mohamed Tabaa; Camille Diou; Rachid Saadane; Abbas Dandache (J. Ubiquitous Syst. Pervasive Networks, 2015)

A comparison of two metaheuristic algorithms for scheduling problem on a heterogeneous CPU/FPGA architecture with communication delays. - Fadel Abdallah; Camel Tanougast; Imed Kacem; Camille Diou; Daniel Singer (CoDIT, 2017)

Formal Proof of the Dependable Bypassing Routing Algorithm Suitable for Adaptive Networks on Chip QnoC Architecture. - Hayat Daoud; Camel Tanougast; Mostefa Belarbi; Mikael Heil; Camille Diou (Syst., 2017)

Genetic algorithms for scheduling in a CPU/FPGA architecture with heterogeneous communication delays. - Fadel Abdallah; Camel Tanougast; Imed Kacem; Camille Diou; Daniel Singer (Comput. Ind. Eng., 2019)

Time-shift immunity for wireless sensor network based on discrete wavelet packets. - Christophe Hüseyin Kizil; Camille Diou; Camel Tanougast (Ann. des Télécommunications, 2021)

Novel design of reward and epsilon-greedy decay strategy tailored for Q-learning in optimizing local mobile robot path planning. - Marouane Ben-Akka; Camel Tanougast; Camille Diou (Knowl. Based Syst., 2025)