Ultra-Low-Power FDSOI Neural Circuits for Extreme-Edge Neuromorphic Intelligence. - Arianna Rubino; Can Livanelioglu; Ning Qiao; Melika Payvand; Giacomo Indiveri (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 0.0014 mm2, 1.18 TΩ Segmented Duty-Cycled Resistor Replacing Pseudo-Resistor for Neural Recording Interface Circuits. - Can Livanelioglu; Woojun Choi; Donghwan Kim; Jiawei Liao; Rosario M. Incandela; Giorgio Cristiano; Taekwang Jang (VLSI Technology and Circuits, 2022)

An Energy-Efficient Impedance-Boosted Discrete-Time Amplifier Achieving 0.34 Noise Efficiency Factor and 389 MΩ Input Impedance. - Gabriele Atzeni; Can Livanelioglu; Lavinia Recchioni; Sina Arjmandpour; Taekwang Jang (VLSI Technology and Circuits, 2023)

A 1, 024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing. - Woojun Choi; Yiyang Chen; Donghwan Kim; Sean Weaver; Tilman Schlotter; Can Livanelioglu; Jiawei Liao; Rosario M. Incandela; Parham Davami; Gabriele Atzeni; Sina Arjmandpour; SeongHwan Cho; et al. (VLSI Technology and Circuits, 2023)

An Impedance-Boosted Transformer-First Discrete-Time Analog Front-End Achieving 0.34 NEF and 389-MΩ Input Impedance. - Gabriele Atzeni; Can Livanelioglu; Sina Arjmandpour; Taekwang Jang (IEEE J. Solid State Circuits, 2024)

A 3.47 NEF 175.2dB FOMs Direct Digitization Front-End Featuring Delta Amplification for Enhanced Dynamic Range and Energy Efficiency in Bio-Signal Acquisition. - Kyeongwon Jeong; Can Livanelioglu; Jiawei Liao; Inhee Lee 001; Taekwang Jang (ISSCC, 2025)

19.10 A 4.6GHz 63.3fsrms PLL-XO Co-Design Using a Self-Aligned Pulse-Injection Driver Achieving -255.2dB FoMJ Including the XO Power and Noise. - Can Livanelioglu; Long He; Jiang Gong; Sina Arjmandpour; Gabriele Atzeni; Taekwang Jang (ISSCC, 2025)