A 16-GB/S 0-DB Power Back-Off 16-QAM Transmitter at 28 GHZ in 65-NM CMOS. - Xiangyu Meng 003; Can Wang 009; Milad Kalantari; C. Patrick Yue (VLSI Circuits, 2018)

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator. - Zhao Zhang 004; Guang Zhu; Can Wang 009; Li Wang 083; C. Patrick Yue (A-SSCC, 2019)

A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. - Can Wang 009; Guang Zhu; Zhao Zhang 004; C. Patrick Yue (VLSI Circuits, 2019)

A Real-Time RGB PAM-4 Visible Light Communication System Based on a Transceiver Design with Pre- and Post-equalizations. - Jian Kang; Xuanzheng Wang; Li Wang 083; Can Wang 009; C. Patrick Yue (MLICOM, 2020)

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator. - Zhao Zhang 004; Guang Zhu; Can Wang 009; Li Wang 083; C. Patrick Yue (IEEE J. Solid State Circuits, 2020)

A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. - Can Wang 009; Li Wang 083; Zhao Zhang 004; Milad Kalantari Mahmoudabadi; Weimin Shi; C. Patrick Yue (IEEE Open J. Circuits Syst., 2021)

Sensing and Cancellation Circuits for Mitigating EMI-Related Common Mode Noise in High-Speed PAM-4 Transmitter. - Rehan Azmat; Li Wang 083; Khawaja Qasim Maqbool; Can Wang 009; C. Patrick Yue (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR. - Li Wang 083; Zhao Zhang 004; Can Wang 009; Rehan Azmat; Weimin Shi; C. Patrick Yue (IEEE J. Solid State Circuits, 2024)