Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (ISPACS, 2011)

Low power secure CSSAL bit-parallel multiplier over GF(24) in 0.18μm CMOS technology. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (ECCTD, 2013)

DPA resistance of charge-sharing symmetric adiabatic logic. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (ISCAS, 2013)

Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (TSP, 2013)

Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (Microelectron. J., 2013)

Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (APCCAS, 2014)

An LSI implementation of a bit-parallel cellular multiplier over GF(24) using secure charge-sharing symmetric adiabatic logic. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (ISCAS, 2014)

Process variation verification of low-power secure CSSAL AES S-box circuit. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (MWSCAS, 2014)

Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (IET Circuits Devices Syst., 2015)

Low Power Source Biased Semi-Adiabatic Logic Circuit for IoT Devices. - Câncio Monteiro; Apolinario Maria; Yasuhiro Takahashi (ISPACS, 2018)

Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices. - Câncio Monteiro; Yasuhiro Takahashi (Sensors, 2021)