An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin. - Cangsang Zhao; Uddalak Bhattacharya; Martin Denham; Jim Kolousek; Yi Lu; Yong-Gee Ng; Novat Nintunze; Kamal Sarkez; Hemmige D. Varadarajan (IEEE J. Solid State Circuits, 1999)

AC IO Loopback Design for High Speed µProcessor IO Test. - Benoit Provost; Chee How Lim; Mo Bashir; Ali Muhtaroglu; Tiffany Huang; Kathy Tian; Mubeen Atha; Cangsang Zhao; Harry Muljono (ITC, 2004)

On-Die Supply-Resonance Suppression Using Band-Limited Active Damping. - Jianping Xu; Peter Hazucha; Mingwei Huang; Paolo A. Aseron; Fabrice Paillet; Gerhard Schrom; James W. Tschanz; Cangsang Zhao; Vivek De; Tanay Karnik; Greg Taylor (ISSCC, 2007)