CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications. - Ghavam G. Shahidi; James D. Warnock; James Comfort; Stephen E. Fischer; Patricia A. McFarland; Alexandre Acovic; Terry I. Chappell; Barbara A. Chappell; Tak H. Ning; Carl J. Anderson; Robert H. Dennard; Jack Y.-C. Sun; et al. (IBM J. Res. Dev., 1995)

Floating body effects in partially-depleted SOI CMOS circuits. - Pong-Fei Lu; Jin Ji; Ching-Te Chuang; Lawrence F. Wagner; Chang-Ming Hsieh; Jente Benedict Kuang; L. Hsu; Mario M. Pelella Jr.; Shao-Fu Sanford Chu; Carl J. Anderson (ISLPED, 1996)

Floating-body effects in partially depleted SOI CMOS circuits. - Pong-Fei Lu; Ching-Te Chuang; Jin Ji; Lawrence F. Wagner; Chang-Ming Hsieh; Jente B. Kuang; Louis Lu-Chen Hsu; Mario M. Pelella Jr.; Shao-Fu Sanford Chu; Carl J. Anderson (IEEE J. Solid State Circuits, 1997)

A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. - Charles F. Webb; Carl J. Anderson; Leon J. Sigal; Kenneth L. Shepard; John S. Liptay; James D. Warnock; Brian W. Curran; Barry Krumm; Mark D. Mayo; Peter J. Camporese; Eric M. Schwarz; Mark S. Farrell; et al. (IEEE J. Solid State Circuits, 1997)

SOI for digital CMOS VLSI: design considerations and advances. - Ching-Te Chuang; Pong-Fei Lu; Carl J. Anderson (Proc. IEEE, 1998)

The circuit and physical design of the POWER4 microprocessor. - James D. Warnock; John M. Keaty; John G. Petrovick; Joachim G. Clabes; Charles J. Kircher; Byron Krauter; Phillip J. Restle; Brian A. Zoric; Carl J. Anderson (IBM J. Res. Dev., 2002)

Beyond innovation: dealing with the risks and complexity of processor design in 22nm. - Carl J. Anderson (DAC, 2009)

One look into the future of CMOS chip design. - Carl J. Anderson (ISPD, 2009)