Correspondence between Ternary Simulation and Binary Race Analysis in Gate Networks (Extended Summary). - Janusz A. Brzozowski; Carl-Johan H. Seger (ICALP, 1986)

Robust Storage Structures for Crash Recovery. - David J. Taylor; Carl-Johan H. Seger (IEEE Trans. Computers, 1986)

A Characterization of Ternary Simulation of Gate Networks. - Janusz A. Brzozowski; Carl-Johan H. Seger (IEEE Trans. Computers, 1987)

An Optimistic Ternary Simulation of Gate Races. - Carl-Johan H. Seger; Janusz A. Brzozowski (Theor. Comput. Sci., 1988)

A bounded delay race model. - Carl-Johan H. Seger (ICCAD, 1989)

A unified framework for race analysis of asynchronous networks. - Janusz A. Brzozowski; Carl-Johan H. Seger (J. ACM, 1989)

Formal Verification of Digital Circuits Using Symbolic Ternary System Models. - Randal E. Bryant; Carl-Johan H. Seger (CAV, 1990)

A Two-Level Formal Verification Methodology using HOL and COSMOS. - Carl-Johan H. Seger; Jeffrey J. Joyce (CAV, 1991)

Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation. - Randal E. Bryant; Derek L. Beatty; Carl-Johan H. Seger (DAC, 1991)

On the Existence of Speed-Independent Circuits. - Carl-Johan H. Seger (Theor. Comput. Sci., 1991)

Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving. - Jeffrey J. Joyce; Carl-Johan H. Seger (DAC, 1993)

The HOL-Voss System: Model-Checking inside a General-Purpose Theorem-Prover. - Jeffrey J. Joyce; Carl-Johan H. Seger (HUG, 1993)

From Abstract Data Types to Shift Registers: A Case Study in Formal Specification and Verification at Differing Levels of Abstraction using Theorem Proving and Symbolic Simulation. - Sreeranga P. Rajan; Jeffrey J. Joyce; Carl-Johan H. Seger (HUG, 1993)

Verification of the Tamarack-3 Microprocessor in a Hybrid Verification Environment. - Zheng Zhu; Jeffrey J. Joyce; Carl-Johan H. Seger (HUG, 1993)

Composing Symbolic Trajectory Evaluation Results. - Scott Hazelhurst; Carl-Johan H. Seger (CAV, 1994)

The Completeness of a Hardware Inference System. - Zheng Zhu; Carl-Johan H. Seger (CAV, 1994)

Automatic Verification of Refinement. - Trevor Wing Sang Lee; Mark R. Greenstreet; Carl-Johan H. Seger (ICCD, 1994)

Digital Circuit Verification Using Partially-Ordered State Models. - Carl-Johan H. Seger; Randal E. Bryant (ISMVL, 1994)

Generalized Ternary Simulation of Sequential Circuits. - Carl-Johan H. Seger; Janusz A. Brzozowski (RAIRO Theor. Informatics Appl., 1994)

Asynchronous Circuits. - Janusz A. Brzozowski; Carl-Johan H. Seger (Springer, 1995)

The formal verification of a pipelined double-precision IEEE floating-point multiplier. - Mark D. Aagaard; Carl-Johan H. Seger (ICCAD, 1995)

Automatic Verification of Asynchronous Circuits. - Trevor Wing Sang Lee; Mark R. Greenstreet; Carl-Johan H. Seger (IEEE Des. Test Comput., 1995)

Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories. - Carl-Johan H. Seger; Randal E. Bryant (Formal Methods Syst. Des., 1995)

A simple theorem prover based on symbolic trajectory evaluation and BDD's. - Scott Hazelhurst; Carl-Johan H. Seger (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Self-Consistency Checking. - Robert B. Jones; Carl-Johan H. Seger; David L. Dill (FMCAD, 1996)

Symbolic Trajectory Evaluation. - Scott Hazelhurst; Carl-Johan H. Seger (Formal Hardware Verification, 1997)

Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment. - Mark D. Aagaard; Robert B. Jones; Carl-Johan H. Seger (DAC, 1998)

Formal Methods in CAD from an Industrial Perspective (abstract). - Carl-Johan H. Seger (FMCAD, 1998)

From lattices to practical formal hardware verification. - Carl-Johan H. Seger (PROCOMET, 1998)

Parametric Representations of Boolean Constraints. - Mark D. Aagaard; Robert B. Jones; Carl-Johan H. Seger (DAC, 1999)

Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving. - Mark D. Aagaard; Robert B. Jones; Carl-Johan H. Seger (TPHOLs, 1999)

Model Checking Lattices: Using and reasoning about information orders for abstraction. - Scott Hazelhurst; Carl-Johan H. Seger (Log. J. IGPL, 1999)

Connecting Bits with Floating-Point Numbers: Model Checking and Theorem Proving in Practice. - Carl-Johan H. Seger (CADE, 2000)

Formal verification of iterative algorithms in microprocessors. - Mark D. Aagaard; Robert B. Jones; Roope Kaivola; Katherine R. Kohatsu; Carl-Johan H. Seger (DAC, 2000)

A Methodology for Large-Scale Hardware Verification. - Mark D. Aagaard; Robert B. Jones; Thomas F. Melham; John W. O'Leary; Carl-Johan H. Seger (FMCAD, 2000)

Combining functional programming and hardware verification (abstract of invited talk). - Carl-Johan H. Seger (ICFP, 2000)

CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. - John Moondanos; Carl-Johan H. Seger; Ziyad Hanna; Daher Kaiss (CAV, 2001)

Practical Formal Verification in Microprocessor Design. - Robert B. Jones; John W. O'Leary; Carl-Johan H. Seger; Mark D. Aagaard; Thomas F. Melham (IEEE Des. Test Comput., 2001)

Generalized Symbolic Trajectory Evaluation - Abstraction in Action. - Jin Yang 006; Carl-Johan H. Seger (FMCAD, 2002)

Introduction to generalized symbolic trajectory evaluation. - Jin Yang 006; Carl-Johan H. Seger (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Compositional Specification and Model Checking in GSTE. - Jin Yang 006; Carl-Johan H. Seger (CAV, 2004)

An industrially effective environment for formal hardware verification. - Carl-Johan H. Seger; Robert B. Jones; John W. O'Leary; Thomas F. Melham; Mark D. Aagaard; Clark W. Barrett; Don Syme (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Automatic Abstraction in Symbolic Trajectory Evaluation. - Sara Adams; Magnus Björk; Thomas F. Melham; Carl-Johan H. Seger (FMCAD, 2007)

Word-Level Symbolic Trajectory Evaluation. - Supratik Chakraborty; Zurab Khasidashvili; Carl-Johan H. Seger; Rajkumar Gajavelly; Tanmay Haldankar; Dinesh Chhatani; Rakesh Mistry (CAV (2), 2015)

Symbolic trajectory evaluation for word-level verification: theory and implementation. - Supratik Chakraborty; Zurab Khasidashvili; Carl-Johan H. Seger; Rajkumar Gajavelly; Tanmay Haldankar; Dinesh Chhatani; Rakesh Mistry (Formal Methods Syst. Des., 2017)

Cephalopode: A custom processor aimed at functional language execution for IoT devices. - Jeremy Pope; Jules Saget; Carl-Johan H. Seger (MEMOCODE, 2020)

Stately: An FSM Design Tool. - Jeremy Pope; Jules Saget; Carl-Johan H. Seger (MEMOCODE, 2020)

Formal Verification of Complex Data Paths: An Industrial Experience. - Carl-Johan H. Seger (FM, 2021)

Bifröst: Creating Hardware With Building Blocks. - Jeremy Pope; Carl-Johan H. Seger (FDL, 2023)

Higher-order Hardware: Implementation and Evaluation of the Cephalopode Graph Reduction Processor. - Jeremy Pope; Carl-Johan H. Seger; Henrik Valter (MEMOCODE, 2024)