A multiplexer-based architecture for high-density, low-power gate arrays. - Robert J. Landers; Shivaling S. Mahant-Shetti; Carl Lemonds (IEEE J. Solid State Circuits, 1995)

Leap frog multiplier. - Shivaling S. Mahant-Shetti; Carl Lemonds; Poras T. Balsara (ISLPED, 1996)

A 1-V programmable DSP for wireless communications [CMOS]. - Wai Lee; Paul E. Landman; Brock Barton; Shigeshi Abiko; Hiroshi Takahashi; Hiroyuki Mizuno; Shigetoshi Muramatsu; Kenichi Tashiro; Masahiro Fusumada; Luat Pham; Frederic Boutaud; Emmanuel Ego; et al. (IEEE J. Solid State Circuits, 1997)

High performance low power array multiplier using temporal tiling. - Shivaling S. Mahant-Shetti; Poras T. Balsara; Carl Lemonds (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Floating-point division algorithms for an x86 microprocessor with a rectangular multiplier. - Michael J. Schulte; Dimitri Tan; Carl Lemonds (ICCD, 2007)

Bridge Floating-Point Fused Multiply-Add Design. - Eric Quinnell; Earl E. Swartzlander Jr.; Carl Lemonds (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support. - Dimitri Tan; Carl Lemonds; Michael J. Schulte (IEEE Trans. Computers, 2009)