An Incremental Garbage Collection Algorithm for Multi-Mutator Systems. - Carl Pixley (Distributed Comput., 1988)

Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence. - Carl Pixley (CAV, 1990)

A Computation Theory and Implementation of Sequential Hardware Equivalence. - Carl Pixley (CAV (DIMACS/AMS volume), 1990)

Calculating Resetability and Reset Sequences. - Carl Pixley; Gary Beihl (ICCAD, 1991)

Automatic Derivation of FSM Specification to Implementation Encoding. - Carl Pixley; Gary Beihl; Ernesto Pacas-Skewes (ICCD, 1991)

Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams. - Carl Pixley; Seh-Woong Jeong; Gary D. Hachtel (DAC, 1992)

A theory and implementation of sequential hardware equivalence. - Carl Pixley (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Minimum Length Synchronizing Sequences of Finite State Machine. - June-Kyung Rho; Fabio Somenzi; Carl Pixley (DAC, 1993)

Synchronizing sequences and symbolic traversal techniques in test generation. - Hyunwoo Cho; Seh-Woong Jeong; Fabio Somenzi; Carl Pixley (J. Electron. Test., 1993)

The Verifiacation Problem for Safe Replaceability. - Vigyan Singhal; Carl Pixley (CAV, 1994)

Multi-level synthesis for safe replaceability. - Carl Pixley; Vigyan Singhal; Adnan Aziz; Robert K. Brayton (ICCAD, 1994)

Exact calculation of synchronizing sequences based on binary decision diagrams. - Carl Pixley; Seh-Woong Jeong; Gary D. Hachtel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

The Validity of Retiming Sequential Circuits. - Vigyan Singhal; Carl Pixley; Richard L. Rudell; Robert K. Brayton (DAC, 1995)

Exploiting power-up delay for sequential optimization. - Vigyan Singhal; Carl Pixley; Adnan Aziz; Robert K. Brayton (EURO-DAC, 1995)

Power-Up Delay for Retiming Digital Circuits. - Vigyan Singhal; Robert K. Brayton; Carl Pixley (ISCAS, 1995)

Commercial Design Verification: Methodology and Tools. - Carl Pixley; Noel R. Strader; William C. Bruce; Jaehong Park; Matt Kaufmann; Kurt Shultz; Michael Burns; Jainendra Kumar; Jun Yuan 007; Janet Nguyen (ITC, 1996)

Formal Verification of FIRE: A Case Study. - Jae-Young Jang; Shaz Qadeer; Matt Kaufmann; Carl Pixley (DAC, 1997)

Intertwined Development and Formal Verification of a 60x Bus Model. - Matt Kaufmann; Carl Pixley (ICCD, 1997)

Logic and Functional Verification in a Commercial Semiconductor Environment. - Jainendra Kumar; Carl Pixley (ACSD, 1998)

Design Constraints in Symbolic Model Checking. - Matt Kaufmann; Andrew Martin; Carl Pixley (CAV, 1998)

Approximate reachability don't cares for CTL model checking. - In-Ho Moon; Jae-Young Jang; Gary D. Hachtel; Fabio Somenzi; Jun Yuan 007; Carl Pixley (ICCAD, 1998)

Modeling design constraints and biasing in simulation using BDDs. - Jun Yuan 007; Kurt Shultz; Carl Pixley; Hillel Miller; Adnan Aziz (ICCAD, 1999)

Integrated Formal and Informal Design Verification of Commercial Integrated Circuits. - Carl Pixley; Kurt Shultz; Jun Yuan 007 (PDPTA, 1999)

Model Checking: A Hardware Design Perspective. - Carl Pixley; Vigyan Singhal (Int. J. Softw. Tools Technol. Transf., 1999)

An Efficient Logic Equivalence Checker for Industrial Circuits. - Jaehong Park; Carl Pixley; Michael Burns; Hyunwoo Cho (J. Electron. Test., 2000)

Automatic Vector Generation Using Constraints and Biasing. - Jun Yuan 007; Kurt Shultz; Carl Pixley; Hillel Miller; Adnan Aziz (J. Electron. Test., 2000)

Experience with term level modeling and verification of the M*CORE TM microprocessor core. - Shuvendu K. Lahiri; Carl Pixley; Ken Albin (HLDVT, 2001)

Application of Formal Verification to Design Creation and Implementation. - Noel R. Strader; Gérard Memmi; Carl Pixley (ISQED, 2001)

Guest Editor's Introduction: Formal Verification of Commercial Integrated Circuits. - Carl Pixley (IEEE Des. Test Comput., 2001)

Theory of safe replacements for sequential circuits. - Vigyan Singhal; Carl Pixley; Adnan Aziz; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Simplifying Circuits for Formal Verification Using Parametric Representation. - In-Ho Moon; Hee-Hwan Kwak; James H. Kukula; Thomas R. Shiple; Carl Pixley (FMCAD, 2002)

Simplifying Constraint Solving in Random Simulation Generation. - Jun Yuan 007; Ken Albin; Adnan Aziz; Carl Pixley (IWLS, 2002)

Formal verification - prove it or pitch it. - Rajesh K. Gupta 001; Shishpal Rawat; Sandeep K. Shukla; Brian Bailey; Daniel K. Beece; Masahiro Fujita; Carl Pixley; John O'Leary; Fabio Somenzi (DAC, 2003)

Constraint synthesis for environment modeling in functional verification. - Jun Yuan 007; Ken Albin; Adnan Aziz; Carl Pixley (DAC, 2003)

A Framework for Constrained Functional Verification. - Jun Yuan 007; Carl Pixley; Adnan Aziz; Ken Albin (ICCAD, 2003)

Panel Summaries. - Carl Pixley; Juan Antonio Carballo (IEEE Des. Test Comput., 2003)

Sequential optimization in the absence of global reset. - Vigyan Singhal; Carl Pixley; Adnan Aziz; Shaz Qadeer; Robert K. Brayton (ACM Trans. Design Autom. Electr. Syst., 2003)

Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders. - In-Ho Moon; Carl Pixley (FMCAD, 2004)

Designers want proofs - but show me the money. - Carl Pixley; D. Meyers; S. McMaster; A. Chittor (MEMOCODE, 2004)

Guest Editors' Introduction: Exploring Synergies for Design Verification. - Carl Pixley; Sharad Malik (IEEE Des. Test Comput., 2004)

Simplifying Boolean constraint solving for random simulation-vector generation. - Jun Yuan 007; Adnan Aziz; Carl Pixley; Ken Albin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Constructing Efficient Formal Models from High-Level Descriptions Using Symbolic Simulation. - Alfred Kölbl; Carl Pixley (Int. J. Parallel Program., 2005)

Constraint-based verification. - Jun Yuan 007; Carl Pixley; Adnan Aziz (Springer, 2006)

Practical Issues in Sequential Equivalence Checking through Alignability: Handling Don't Cares and Generating Debug Traces. - In-Ho Moon; Per Bjesse; Carl Pixley (HLDVT, 2006)

Panel: Assertion-Based Verification -What's the Big Deal? - Sandeep K. Shukla; Alan J. Hu; Jacob Abrahams; Pranav Ashar; Harry Foster; Avner Landver; Carl Pixley (HLDVT, 2006)

Guest Editors' Introduction: The True State of the Art of ESL Design. - Sandeep K. Shukla; Carl Pixley; Gary Smith 001 (IEEE Des. Test Comput., 2006)

Memory Modeling in ESL-RTL Equivalence Checking. - Alfred Kölbl; Jerry R. Burch; Carl Pixley (DAC, 2007)

A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states. - In-Ho Moon; Per Bjesse; Carl Pixley (DATE, 2007)

Practical Considerations Concerning HL-to -RT Equivalence Checking. - Carl Pixley (Haifa Verification Conference, 2008)

Solver technology for system-level to RTL equivalence checking. - Alfred Kölbl; Reily Jacoby; Himanshu Jain; Carl Pixley (DATE, 2009)