A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. - Heinz Hoenigschmid; Alexander Frey; John K. DeBrosse; Toshiaki Kirihata; Gerhard Mueller; Daniel W. Storaska; Gabriel Daniel; Gerd Frankowsky; Kevin P. Guay; David R. Hanson; Louis Lu-Chen Hsu; Brian Ji; et al. (IEEE J. Solid State Circuits, 2000)

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing. - Azeez J. Bhavnagarwala; Stephen Kosonocky; Carl Radens; Yuen H. Chan; Kevin Stawiasz; Uma Srinivasan 002; Steven P. Kowalczyk; Matthew M. Ziegler (IEEE J. Solid State Circuits, 2008)

A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements. - Harold Pilo; Igor Arsovski; Kevin Batson; Geordie Braceras; John A. Gabric; Robert M. Houle; Steve Lamphier; Frank Pavlik; Adnan Seferagic; Liang-Yu Chen; Shang-Bin Ko; Carl Radens (ISSCC, 2011)

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements. - Harold Pilo; Igor Arsovski; Kevin Batson; Geordie Braceras; John A. Gabric; Robert M. Houle; Steve Lamphier; Carl Radens; Adnan Seferagic (IEEE J. Solid State Circuits, 2012)

Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction. - Rajiv V. Joshi; Keunwoo Kim; Rouwaida Kanj; Ajay N. Bhoj; Matthew M. Ziegler; Phil Oldiges; Pranita Kerber; Robert Wong; Terence Hook; Sudesh Saroop; Carl Radens; Chun-Chen Yeh (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM. - Rajiv V. Joshi; Sudesh Saroop; Rouwaida Kanj; Yang Liu; Weike Wang; Carl Radens; Yue Tan; Karthik Yogendra (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM. - Randy W. Mann; Meixiong Zhao; Sanjay Parihar; Qun Gao; Ankur Arya; Carl Radens; Shesh Mani Pandey; Joseph Versaggi; Jack M. Higman; Rick Carter (IEEE Trans. Very Large Scale Integr. Syst., 2019)