TimberWolf3.2: a new standard cell placement and global routing package. - Carl Sechen; Alberto L. Sangiovanni-Vincentelli (DAC, 1986)

Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing. - Carl Sechen (DAC, 1988)

A new global router for row-based layout. - Kai-Win Lee; Carl Sechen (ICCAD, 1988)

An improved objective function for mincut circuit partitioning. - Carl Sechen; Dahe Chen (ICCAD, 1988)

ThunderBird: a complete standard cell layout package. - Carl Sechen; Douglas Braun; Alberto L. Sangiovanni-Vincentelli (IEEE J. Solid State Circuits, 1988)

New Algorithms for the Placement and Routing of Macro Cells. - William Swartz; Carl Sechen (ICCAD, 1990)

Mickey: a macro cell global router. - Dahe Chen; Carl Sechen (EURO-DAC, 1991)

A global router for sea-of-gates circuits. - Kai-Win Lee; Carl Sechen (EURO-DAC, 1991)

Maximum projections of don't care conditions in a Boolean network. - Ted Stanion; Carl Sechen (ICCAD, 1993)

A new generalized row-based global router. - William Swartz; Carl Sechen (ICCAD, 1993)

Generation of color-constrained spanning trees with application in symbolic circuit analysis. - Qicheng Yu; Carl Sechen (Great Lakes Symposium on VLSI, 1994)

A loosely coupled parallel algorithm for standard cell placement. - Wern-Jieh Sun; Carl Sechen (ICCAD, 1994)

Approximate symbolic analysis of large analog integrated circuits. - Qicheng Yu; Carl Sechen (ICCAD, 1994)

Boolean division and factorization using binary decision diagrams. - Ted Stanion; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Quasi-algebraic decompositions of switching functions. - Ted Stanion; Carl Sechen (ARVLSI, 1995)

A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis. - Ted Stanion; Carl Sechen (DAC, 1995)

Timing Driven Placement for Large Standard Cell Circuits. - William Swartz; Carl Sechen (DAC, 1995)

Multiple FPGA Partitioning with Performance Optimization. - Kalapi Roy-Neogi; Carl Sechen (FPGA, 1995)

Accurate Extraction of Simplified Symbolic Pole/Zero Expressions for Large Analog IC's. - Jer-Jaw Hsu; Carl Sechen (ISCAS, 1995)

Efficient Approximation of Symbolic Network Function Using Matroid Intersection Algorithms. - Qicheng Yu; Carl Sechen (ISCAS, 1995)

An efficient method for generating exhaustive test sets. - Ted Stanion; Debashis Bhattacharya; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Efficient and effective placement for very large circuits. - Wern-Jieh Sun; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc. - Bingzhong Guan; Carl Sechen (ICCD, 1996)

Clock-Delayed Domino for Adder and Combinational Logic Desig. - Gin Yee; Carl Sechen (ICCD, 1996)

Generation of colour-constrained spanning trees with application in symbolic circuit analysis. - Qicheng Yu; Carl Sechen (Int. J. Circuit Theory Appl., 1996)

A Sea-of-Gates Style FPGA Placement Algorithm. - Kalapi Roy-Neogi; Bingzhong Guan; Carl Sechen (VLSI Design, 1996)

A Timing-Driven Partitioning System for Multiple FPGAs. - Kalapi Roy-Neogi; Carl Sechen (VLSI Design, 1996)

The Future of Custom Cell Generation in Physical Synthesis. - Martin Lefebvre 001; David Marple; Carl Sechen (DAC, 1997)

Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic. - Le-Chin Eugene Liu; Carl Sechen (ED&TC, 1997)

A gridless multi-layer router for standard cell circuits using CTM cells. - Hsiao-Ping Tseng; Carl Sechen (ED&TC, 1997)

A parallel standard cell placement algorithm. - Wern-Jieh Sun; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Efficient approximation of symbolic network functions using matroid intersection algorithms. - Qicheng Yu; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Domino logic synthesis using complex static gates. - Tyler Thorp; Gin Yee; Carl Sechen (ICCAD, 1998)

Chip-level area routing. - Le-Chin Eugene Liu; Hsiao-Ping Tseng; Carl Sechen (ISPD, 1998)

AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths. - Tatjana Serdar; Carl Sechen (ICCAD, 1999)

Design and Synthesis of Monotonic Circuits. - Tyler Thorp; Gin Yee; Carl Sechen (ICCD, 1999)

Multilayer pin assignment for macro cell circuits. - Le-Chin Eugene Liu; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic. - Le-Chin Eugene Liu; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A gridless multilayer router for standard cell circuits using CTMcells. - Hsiao-Ping Tseng; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A locally-clocked dynamic logic serial/parallel multiplier. - Gregg N. Hoyer; Carl Sechen (CICC, 2000)

Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. - Jovanka Ciric; Gin Yee; Carl Sechen (DATE, 2000)

Output Prediction Logic: A High-Performance CMOS Design Technique. - Larry McMurchie; Su Kio; Gin Yee; Tyler Thorp; Carl Sechen (ICCD, 2000)

An Automated Shielding Algorithm and Tool For Dynamic Circuits. - Gin Yee; Tyler Thorp; Ron Christopherson; Ban P. Wang; Carl Sechen (ISQED, 2000)

Clock-delayed domino for dynamic circuit design. - Gin Yee; Carl Sechen (IEEE Trans. Very Large Scale Integr. Syst., 2000)

A High-Performance 64-bit Adder Implemented in Output Prediction Logic. - Sheng Sun; Larry McMurchie; Carl Sechen (ARVLSI, 2001)

Panel: (When) Will FPGAs Kill ASICs? - Rob A. Rutenbar; Max Baron; Thomas Daniel; Rajeev Jayaraman; Zvi Or-Bach; Jonathan Rose; Carl Sechen (DAC, 2001)

Automatic datapath tile placement and routing. - Tatjana Serdar; Carl Sechen (DATE, 2001)

Timing- and crosstalk-driven area routing. - Hsiao-Ping Tseng; Louis Scheffer; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

WTA: waveform-based timing analysis for deep submicron circuits. - Larry McMurchie; Carl Sechen (ICCAD, 2002)

Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. - Hiran Tennakoon; Carl Sechen (ICCAD, 2002)

Optimized Power-Delay Curve Generation for Standard Cell ICs. - Miodrag Vujkovic; Carl Sechen (IWLS, 2002)

Locally clocked pipelines and dynamic logic. - Gregg N. Hoyer; Gin Yee; Carl Sechen (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Libraries: lifejacket or straitjacket. - Carl Sechen; Barbara Chappel; Jim Hogan; Andrew Moore; Tadahiko Nakamura; Gregory A. Northrop; Anjaneya Thakar (DAC, 2003)

A low power delayed-clocks generation and distribution system. - Su Kio; Kian Haur Chong; Carl Sechen (ISCAS (5), 2003)

Efficient canonical form for Boolean matching of complex functions in large libraries. - Jovanka Ciric; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Design and synthesis of dynamic circuits. - T. J. Thorp; G. S. Yee; Carl M. Sechen (IEEE Trans. Very Large Scale Integr. Syst., 2003)

A high performance CMOS programmable logic core. - Yi Han; Larry McMurchie; Carl Sechen (CICC, 2004)

Efficient timing closure without timing driven placement and routing. - Miodrag Vujkovic; David Wadkins; William Swartz; Carl Sechen (DAC, 2004)

A high throughput divider implementation. - Xinyu Guo; Carl Sechen (CICC, 2005)

Efficient and accurate gate sizing with piecewise convex delay models. - Hiran Tennakoon; Carl Sechen (DAC, 2005)

High Speed Redundant Adder and Divider in Output Prediction Logic. - Xinyu Guo; Carl Sechen (ISVLSI, 2005)

409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS. - Sheng Sun; Yi Han; Xinyu Guo; Kian Haur Chong; Larry McMurchie; Carl Sechen (ISVLSI, 2005)

Efficient Post-layout Power-Delay Curve Generation. - Miodrag Vujkovic; David Wadkins; Carl Sechen (PATMOS, 2005)

Post-layout energy-delay analysis of parallel multipliers. - Jinyao Zhang; Miodrag Vujkovic; David Wadkins; Carl Sechen (ISCAS, 2006)

A 64b adder using self-calibrating differential output prediction logic. - Kian Haur Chong; Larry McMurchie; Carl Sechen (ISSCC, 2006)

Post-layout comparison of high performance 64b static adders in energy-delay space. - Sheng Sun; Carl Sechen (ICCD, 2007)

Nonconvex Gate Delay Modeling and Delay Optimization. - Hiran Tennakoon; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Power reduction via separate synthesis and physical libraries. - Mohammad Rahman; Ryan Afonso; Hiran Tennakoon; Carl Sechen (DAC, 2011)

Power reduction via near-optimal library-based cell-size selection. - Mohammad Rahman; Hiran Tennakoon; Carl Sechen (DATE, 2011)

Power efficient partial product compression. - Chiu-wei Pan; Zhao Wang; Yuanchen Song; Carl Sechen (ACM Great Lakes Symposium on VLSI, 2011)

Post-synthesis leakage power minimization. - Mohammad Rahman; Carl Sechen (DATE, 2012)

Low-voltage low-overhead asynchronous logic. - Akshay Sridharan; Carl Sechen; Roozbeh Jafari (ISLPED, 2013)

Library-Based Cell-Size Selection Using Extended Logical Effort. - Mohammad Rahman; Hiran Tennakoon; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

TonyChopper: a desynchronization package. - Zhao Wang; Xiao He; Carl M. Sechen (ICCAD, 2014)

A New Approach for Gate-Level Delay-Insensitive Asynchronous Logic. - Zhao Wang; Xiao He; Carl Sechen (Circuits Syst. Signal Process., 2015)

11.1 Dual-MEMS-resonator temperature-to-digital converter with 40 K resolution and FOM of 0.12pJK2. - Meisam Heidarpour Roshan; Samira Zali Asl; Kimo Joo; Kamran Souri; Rajkumar Palwai; Lijun Will Chen; Sudhakar Pamarti; Joseph C. Doll; Nicholas Miller; Carl Arft; Sassan Tabatabaei; Carl Sechen; et al. (ISSCC, 2016)

Are standalone gate size and VT optimization tools useful? - Anitha Kumari Yella; Gunturi Srivatsa; Carl Sechen (CCECE, 2017)

A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration. - Jingxiang Tian; Gaurav Rajavendra Reddy; Jiajia Wang; William Swartz; Yiorgos Makris; Carl Sechen (DATE, 2017)

On designing optimal camouflaged layouts. - Thomas Broadfoot; Carl Sechen; Jeyavijayan (JV) Rajendran (HOST, 2017)

A MEMS-Assisted Temperature Sensor With 20-µK Resolution, Conversion Rate of 200 S/s, and FOM of 0.04 pJK2. - Meisam Heidarpour Roshan; Samira Zaliasl; Kimo Joo; Kamran Souri; Rajkumar Palwai; Lijun Will Chen; Amanpreet Singh; Sudhakar Pamarti; Nicholas Miller; Joseph C. Doll; Carl Arft; Sassan Tabatabaei; et al. (IEEE J. Solid State Circuits, 2017)

Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. - Tutu Ajayi; Vidya A. Chhabria; Mateus Fogaça; Soheil Hashemi; Abdelrahman Hosny; Andrew B. Kahng; Minsoo Kim; Jeongsup Lee; Uday Mallappa; Marina Neseem; Geraldo Pradipta; Sherief Reda; et al. (DAC, 2019)

Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming. - Mustafa M. Shihab; Jingxiang Tian; Gaurav Rajavendra Reddy; Bo Hu; William Swartz; Benjamin Carrión Schäfer; Carl Sechen; Yiorgos Makris (DATE, 2019)

Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA. - Bo Hu; Jingxiang Tian; Mustafa M. Shihab; Gaurav Rajavendra Reddy; William Swartz; Yiorgos Makris; Benjamin Carrión Schäfer; Carl Sechen (ACM Great Lakes Symposium on VLSI, 2019)

Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage. - Bo Hu; Mustafa M. Shihab; Yiorgos Makris; Benjamin Carrión Schäfer; Carl Sechen (FPT, 2019)

An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs. - Bo Hu; Mustafa M. Shihab; Yiorgos Makris; Benjamin Carrión Schäfer; Carl Sechen (DATE, 2020)

Optimal Standard Cell Library Composition for 7nm. - Vibhav Kumarswami Salimath; Carl Sechen (ISCAS, 2020)

CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric. - Mustafa M. Shihab; Bharath Ramanidharan; Gaurav Rajavendra Reddy; Jingxiang Tian; William Swartz; Carl Sechen; Yiorgos Makris (ISCAS, 2020)

ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric. - Mustafa Munawar Shihab; Bharath Ramanidharan; Suraag Sunil Tellakula; Gaurav Rajavendra Reddy; Jingxiang Tian; Carl Sechen; Yiorgos Makris (VTS, 2020)

Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric. - Apurva Jain; Thomas Broadfoot; Yiorgos Makris; Carl Sechen (DATE, 2023)

Testing a Transistor-Level Programmable Fabric: Challenges and Solutions. - Apurva Jain; Thomas Broadfoot; Carl Sechen; Yiorgos Makris (VTS, 2024)

A TRAP for SAT: On the Imperviousness of a Transistor-Level Programmable Fabric to Satisfiability-Based Attacks. - Aric Fowler; Mohammed Shayan; Mustafa M. Shihab; Thomas Broadfoot; Peter Beerel; Carl Sechen; Yiorgos Makris (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

Modeling Bidirectional Switches for Enabling Logic Equivalence Checking in a Transistor-Level Programmable Fabric. - Apurva Jain; Thomas Broadfoot; Yiorgos Makris; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)