A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique. - Carlos Briseno-Vidrios; Alexander Edward; Ayman Shafik; Samuel Palermo; José Silva-Martínez (VLSIC, 2015)

A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer. - Carlos Briseno-Vidrios; Alexander Edward; Negar Rashidi; José Silva-Martínez (IEEE J. Solid State Circuits, 2016)

A 13bit 200MS/S pipeline ADC with current-mode MDACs. - Carlos Briseno-Vidrios; Dadian Zhou; Suraj Prakash; Qiyuan Liu 001; Alexander Edward; José Silva-Martínez (ISCAS, 2017)

High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications. - Qiyuan Liu 001; Alexander Edward; Carlos Briseno-Vidrios; Negar Rashidi; José Silva-Martínez (MWSCAS, 2017)

A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage. - Carlos Briseno-Vidrios; Alexander Edward; Ayman Shafik; Samuel Palermo; José Silva-Martínez (IEEE J. Solid State Circuits, 2017)

A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS. - Alexander Edward; Qiyuan Liu 001; Carlos Briseno-Vidrios; Martin Kinyua; Eric G. Soenen; Aydin Ilker Karsilayan; José Silva-Martínez (IEEE J. Solid State Circuits, 2017)

Low-Power Gm-C Filter Employing Current-Reuse Differential Difference Amplifiers. - John S. Mincey; Carlos Briseno-Vidrios; José Silva-Martínez; Christopher T. Rodenbeck (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs. - Carlos Briseno-Vidrios; Dadian Zhou; Suraj Prakash; Qiyuan Liu 001; Alexander Edward; Eric G. Soenen; Martin Kinyua; José Silva-Martínez (IEEE J. Solid State Circuits, 2018)

A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration. - Dadian Zhou; Carlos Briseno-Vidrios; Junning Jiang; Chulhyun Park; Qiyuan Liu 001; Eric G. Soenen; Martin Kinyua; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)