Analytic Model of a Cache Only Memory Architecture. - Carlos Carreras; Carlos A. López Bario; Manuel V. Hermenegildo (PARLE, 1994)

A Co-Design Methodology Based on Formal Specification and High-level Estimation. - Carlos Carreras; Juan Carlos López 001; María Luisa López Vallejo; Luis Sánchez 001; Carlos Delgado Kloos; Natividad Martínez Madrid (CODES, 1996)

Bit-Width Selection for Data-Path Implementations. - Carlos Carreras; Juan A. López; Octavio Nieto-Taladriz (ISSS, 1999)

Grid-Based Histogram Arithmetic for the Probabilistic Analysis of Functions. - Carlos Carreras; Manuel V. Hermenegildo (SARA, 2000)

On interval methods applied to robot reliability quantification. - Carlos Carreras; Ian D. Walker (Reliab. Eng. Syst. Saf., 2000)

Interval methods for fault-tree analysis in robotics. - Carlos Carreras; Ian D. Walker (IEEE Trans. Reliab., 2001)

Fast characterization of the noise bounds derived from coefficient and signal quantization. - Juan A. López; Carlos Carreras; Gabriel Caffarena; Octavio Nieto-Taladriz (ISCAS (4), 2003)

Fixed-point refinement of OFDM-based adaptive equalizers: An heuristic approach. - Gabriel Caffarena; Angel Fernández; Carlos Carreras; Octavio Nieto-Taladriz (EUSIPCO, 2004)

Analysis of limit cycles by means of affine arithmetic computer-aided tests. - Juan A. López; Gabriel Caffarena; Carlos Carreras; Octavio Nieto-Taladriz (EUSIPCO, 2004)

A Generator of High-Speed Floating-Point Modules. - Gerardo Leyva; Gabriel Caffarena; Carlos Carreras; Octavio Nieto-Taladriz (FCCM, 2004)

Extension versus bending for continuum robots. - Robin McDonnell; George Grimes; Ian D. Walker; Carlos Carreras (ICINCO, 2005)

High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs. - Gabriel Caffarena; Juan A. López; Carlos Carreras; Octavio Nieto-Taladriz (FPL, 2006)

Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources. - Gabriel Caffarena; Juan A. López; Carlos Carreras; Octavio Nieto-Taladriz (SoC, 2006)

Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits. - Gabriel Caffarena; George A. Constantinides; Peter Y. K. Cheung; Carlos Carreras; Octavio Nieto-Taladriz (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Switching Activity Models for Power Estimation in FPGA Multipliers. - Ruzica Jevtic; Carlos Carreras; Gabriel Caffarena (ARC, 2007)

A TCP/IP Fragmentation Monitoring Core For Intrusion Prevention. - Vukasin Pejovic; Slobodan Bojanic; Carlos Carreras (ERSA, 2007)

Adding Value to TCP/IP Based Information exchange Security by Specialized Hardware. - Vukasin Pejovic; Slobodan Bojanic; Carlos Carreras (SECURWARE, 2007)

Fpga Acceleration for DNA Sequence Alignment. - Gabriel Caffarena; Carlos E. Pedreira; Carlos Carreras; Slobodan Bojanic; Octavio Nieto-Taladriz (J. Circuits Syst. Comput., 2007)

Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops. - Juan A. López; Carlos Carreras; Octavio Nieto-Taladriz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Analytical High-Level Power Model for LUT-Based Components. - Ruzica Jevtic; Carlos Carreras (PATMOS, 2008)

Optimized Architectural Synthesis of Fixed-Point Datapaths. - Gabriel Caffarena; Juan A. López; Gerardo Leyva; Carlos Carreras; Octavio Nieto-Taladriz (ReConFig, 2008)

A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components. - Ruzica Jevtic; Carlos Carreras; Domenik Helms (ReConFig, 2008)

Fast and accurate computation of the roundoff noise of linear time-invariant systems. - Juan A. López; Gabriel Caffarena; Carlos Carreras; Octavio Nieto-Taladriz (IET Circuits Devices Syst., 2008)

Behavioural Biometrics Hardware Based on Bioinformatics Matching. - Slobodan Bojanic; Vukasin Pejovic; Gabriel Caffarena; Vladimir M. Milovanovic; Carlos Carreras; Jelena Popovic (CISIS, 2009)

A Practical Method for Testing High-Speed Networking Hardware Architectures. - Vukasin Pejovic; Slobodan Bojanic; Carlos Carreras; Atta Badii (ICNS, 2009)

Floorplan-based FPGA interconnect power estimation in DSP circuits. - Ruzica Jevtic; Carlos Carreras; Vukasin Pejovic (SLIP, 2009)

Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs. - Gabriel Caffarena; Juan A. López; Gerardo Leyva; Carlos Carreras; Octavio Nieto-Taladriz (Int. J. Reconfigurable Comput., 2009)

Precision-wise architectural synthesis of DSP circuits. - Gabriel Caffarena; Carlos Carreras (EUSIPCO, 2010)

SQNR estimation of non-linear fixed-point algorithms. - Gabriel Caffarena; Juan A. López; Angel Fernandez Herrero; Carlos Carreras (EUSIPCO, 2010)

Architectural synthesis of DSP circuits under simultaneous error and time constraints. - Gabriel Caffarena; Carlos Carreras (VLSI-SoC, 2010)

Fast fixed-point optimization of DSP algorithms. - Gabriel Caffarena; Carlos Carreras; Juan A. López; Angel Fernandez Herrero (VLSI-SoC, 2010)

SQNR Estimation of Fixed-Point DSP Algorithms. - Gabriel Caffarena; Carlos Carreras; Juan A. López; Angel Fernandez Herrero (EURASIP J. Adv. Signal Process., 2010)

A Multistandard Frequency Offset Synchronization Scheme for 802.11n, 802.16d, LTE, and DVB-T/H Systems. - Javier Gonzalez Bayon; Carlos Carreras; Ove Edfors (J. Comput. Networks Commun., 2010)

Improved schemes for tracking residual frequency offset in DVB-T systems. - Javier Gonzalez Bayon; Angel Fernandez Herrero; Carlos Carreras (IEEE Trans. Consumer Electron., 2010)

Power Estimation of Embedded Multiplier Blocks in FPGAs. - Ruzica Jevtic; Carlos Carreras (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Power estimation of dividers implemented in FPGAs. - Ruzica Jevtic; Bojan Jovanovic; Carlos Carreras (ACM Great Lakes Symposium on VLSI, 2011)

Mesh traversal and sorting for efficient memory usage in scientific codes. - Pablo Barrio 001; Carlos Carreras (IPCCC, 2011)

Power Measurement Methodology for FPGA Devices. - Ruzica Jevtic; Carlos Carreras (IEEE Trans. Instrum. Meas., 2011)

Turning control flow graphs into function calls: Code generation for heterogeneous architectures. - Pablo Barrio 001; Carlos Carreras; Roberto Sierra; Tobias Kenter; Christian Plessl (HPCS, 2012)

A reduced complexity scheme for carrier frequency synchronization in uplink 802.16e OFDMA. - Javier Gonzalez Bayon; Angel Fernandez Herrero; Carlos Carreras (EURASIP J. Adv. Signal Process., 2012)

A complete dynamic power estimation model for data-paths in FPGA DSP designs. - Ruzica Jevtic; Carlos Carreras (Integr., 2012)

Evaluation of Rapid Prototyping solutions for a 802.16d frequency Offset estimation Scheme. - Javier Gonzalez Bayon; Angel Fernandez Herrero; Carlos Carreras (J. Circuits Syst. Comput., 2012)

Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes. - Pablo Barrio 001; Carlos Carreras; Juan A. López; Óscar Robles; Ruzica Jevtic; Roberto Sierra (J. Syst. Archit., 2014)

Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits. - Bojan Jovanovic; Ruzica Jevtic; Carlos Carreras (IEEE Trans. Ind. Informatics, 2014)

A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors. - Roberto Sierra; Carlos Carreras; Gabriel Caffarena; Carlos A. López Bario (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs. - Roberto Sierra; Carlos Carreras; Gabriel Caffarena (PATMOS, 2018)

High-Performance Decoding of Variable-Length Memory Data Packets for FPGA Stream Processing. - Roberto Sierra; Filippo Mangani; Carlos Carreras; Gabriel Caffarena (FPL, 2019)

Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs. - Roberto Sierra; Carlos Carreras; Gabriel Caffarena (Integr., 2019)