Multilevel simulation-based co-design of next generation HPC microprocessors. - Lilia Zaourar; Mohamed Benazouz; Ayoub Mouhagir; Fatma Jebali; Tanguy Sassolas; Jean-Christophe Weill; Carlos Falquez; Nam Ho; Dirk Pleiter; Antoni Portero; Estela Suarez; Polydoros Petrakis; et al. (PMBS, 2021)

COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores. - Antoni Portero; Carlos Falquez; Nam Ho; Polydoros Petrakis; Stepan Nassyr; Manolis Marazakis; Romain Dolbeau; Jorge Alejandro Nocua Cifuentes; Luis Bertran Alvarez; Dirk Pleiter; Estela Suarez (ARCS, 2023)

Case Studies on the Impact and Challenges of Heterogeneous NUMA Architectures for HPC. - Lilia Zaourar; Mohamed Benazouz; Ayoub Mouhagir; Carlos Falquez; Antoni Portero; Nam Ho; Estela Suarez; Polydoros Petrakis; Manolis Marazakis; Francesco Sgherzi; Ivan Fernandez; Romain Dolbeau; et al. (ARCS, 2024)

Data Prefetching on Processors with Heterogeneous Memory. - Berk Saglam; Nam Ho; Carlos Falquez; Antoni Portero; Fabian Schätzle; Estela Suarez; Dirk Pleiter (MEMSYS, 2024)

Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation. - Fabian Schätzle; Carlos Falquez; Stefan Heinen; Nam Ho; Antoni Portero; Estela Suarez; Johannes Van Den Boom; Stefan van Waasen (RAPIDO@HiPEAC, 2024)

Modeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-based Co-Design. - Fabian Schätzle; Carlos Falquez; Nam Ho; André Zambanini; Johannes Van Den Boom; Estela Suarez (ISC, 2025)

Memory Prefetching Evaluation of Scientific Applications on a Modern HPC Arm-Based Processor. - Nam Ho; Carlos Falquez; Antoni Portero; Estela Suarez; Dirk Pleiter (IEEE Access, 2025)