Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms. - Carlos Flores Fajardo; Zhen Fang 002; Ravi R. Iyer 001; German Fabila Garcia; Seung Eun Lee; Li Zhao 002 (DAC, 2011)

Cost-effectively offering private buffers in SoCs and CMPs. - Zhen Fang 002; Li Zhao 002; Ravishankar R. Iyer 001; Carlos Flores Fajardo; German Fabila Garcia; Seung Eun Lee; Bin Li 018; Steve R. King; Xiaowei Jiang; Srihari Makineni (ICS, 2011)

Visual IoT: Ultra-Low-Power Processing Architectures and Implications. - Vui Seng Chua; Julio Zamora-Esquivel; Anindya Sao Paul; Thawee Techathamnukool; Carlos Flores Fajardo; Nilesh Jain; Omesh Tickoo; Ravi R. Iyer 001 (IEEE Micro, 2017)