VHDL package for description of fuzzy logic controllers. - D. Galán; Carlos Jesús Jiménez-Fernández; Angel Barriga; Santiago Sánchez-Solano (EURO-DAC, 1995)

XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers. - E. Lago; Carlos Jesús Jiménez-Fernández; Diego R. López; Santiago Sánchez-Solano; Angel Barriga (DATE, 1998)

A design methodology for application specific fuzzy integrated circuits. - Angel Barriga; Raouf Senhadji; Carlos Jesús Jiménez-Fernández; Iluminada Baturone; Santiago Sánchez-Solano (ICECS, 1998)

Hardware/software codesign methodology for fuzzy controller implementation. - Alejandro Cabrera; Santiago Sánchez-Solano; Raouf Senhadji; Angel Barriga; Carlos Jesús Jiménez-Fernández (FUZZ-IEEE, 2002)

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. - Carmen Baena Oliva; Jorge Juan-Chico; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; Carlos Jesús Jiménez-Fernández; Manuel Valencia 001 (PATMOS, 2002)

Prototyping of Fuzzy Logic-Based Controllers Using Standard FPGA Development Boards. - Santiago Sánchez-Solano; Raouf Senhadji; Alejandro Cabrera Sarmiento; Iluminada Baturone; Carlos Jesús Jiménez-Fernández; Angel Barriga (IEEE International Workshop on Rapid System Prototyping, 2002)

Logic Synthesis. - Angel Barriga; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (Wiley Encyclopedia of Computer Science and Engineering, 2008)

Low Power Implementation of Trivium Stream Cipher. - José Miguel Mora-Gutierrez; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (PATMOS, 2012)

A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions. - Piedad Brox; Javier Castro-Ramirez; Macarena C. Martínez-Rodríguez; Erica Tena; Carlos Jesús Jiménez-Fernández; Iluminada Baturone; Antonio J. Acosta 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Fault attack on FPGA implementations of Trivium stream cipher. - Francisco Eugenio Potestad-Ordóñez; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (ISCAS, 2016)

Trivium hardware implementations for power reduction. - José Miguel Mora-Gutierrez; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (Int. J. Circuit Theory Appl., 2017)

Power and Energy Issues on Lightweight Cryptography. - Antonio J. Acosta 001; Erica Tena-Sánchez; Carlos Jesús Jiménez-Fernández; Javier M. Mora-Merchan (J. Low Power Electron., 2017)

Multiradix Trivium Implementations for Low-Power IoT Hardware. - José Miguel Mora-Gutierrez; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Vulnerability Analysis of Trivium FPGA Implementations. - Francisco Eugenio Potestad-Ordóñez; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. - Francisco Eugenio Potestad-Ordóñez; Carlos Jesús Jiménez-Fernández; Carmen Baena Oliva; Pilar Parra Fernández; Manuel Valencia-Barrero (DCIS, 2018)

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Ricardo Chaves; Manuel Valencia-Barrero; Antonio Acosta-Jiménez; Carlos Jesús Jiménez-Fernández (ISCAS, 2020)

An Academic Approach to FPGA Design Based on a Distance Meter Circuit. - Carlos Jesús Jiménez-Fernández; Carmen Baena Oliva; Pilar Parra Fernández; Francisco Eugenio Potestad-Ordóñez; Manuel Valencia-Barrero (Rev. Iberoam. de Tecnol. del Aprendiz., 2020)

Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA. - Francisco Eugenio Potestad-Ordóñez; Manuel Valencia-Barrero; Carmen Baena Oliva; Pilar Parra Fernández; Carlos Jesús Jiménez-Fernández (Sensors, 2020)

ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium. - José Miguel Mora-Gutierrez; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (IEEE Trans. Circuits Syst., 2020)

Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; José Miguel Mora-Gutierrez; Manuel Valencia-Barrero; Carlos Jesús Jiménez-Fernández (IEEE Access, 2021)

Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; José Miguel Mora-Gutierrez; Manuel Valencia-Barrero; Carlos Jesús Jiménez-Fernández (Sensors, 2021)

Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Antonio J. Acosta 001; Carlos Jesús Jiménez-Fernández; Ricardo Chaves (IEEE Access, 2022)

Cryptographic Security Through a Hardware Root of Trust. - Luis F. Rojas-Muñoz; Santiago Sánchez-Solano; Macarena C. Martínez-Rodríguez; Eros Camacho-Ruiz; Pablo Navarro-Torrero; Apurba Karmakar; Carlos Fernández García; Erica Tena-Sánchez; Francisco Eugenio Potestad-Ordóñez; Alejandro Casado-Galán; Pau Ortega-Castro; Antonio Acosta-Jiménez; et al. (ARC, 2024)

TinyJAMBU Hardware Implementation for Low Power. - Carlos Fernández García; José Miguel Mora-Gutierrez; Carlos Jesús Jiménez-Fernández (IEEE Access, 2024)