FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations. - Carlos Morra; Jürgen Becker 001; Mauricio Ayala-Rincón; Reiner W. Hartenstein (FPL, 2005)

Configware Design Space Exploration Using Rewriting Logic. - Carlos Morra (FPL, 2006)

From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. - Carlos Morra; M. Sackmann; Sunil Shukla; Jürgen Becker 001; Reiner W. Hartenstein (FPL, 2006)

Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. - Carlos Morra; M. Sackmann; Jürgen Becker 001; Reiner W. Hartenstein (ReCoSoC, 2006)

Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements. - Carlos Morra; João M. P. Cardoso; Jürgen Becker 001 (IPDPS, 2007)

Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures. - Carlos Morra; João Bispo; João M. P. Cardoso; Jürgen Becker 001 (FCCM, 2008)

Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures. - Carlos Morra; João M. P. Cardoso; João Bispo; Jürgen Becker 001 (SASP, 2008)