A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC. - Hyung Seok Kim; Carlos Ornelas; Kailash Chandrashekar; Pin-en Su; Paolo Madoglio; Yee William Li; Ashoke Ravi (ESSCIRC, 2012)

A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS. - Y. William Li; Carlos Ornelas; Hyung Seok Kim; Hasnain Lakdawala; Ashoke Ravi; Krishnamurthy Soumyanath (ISSCC, 2012)

A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique. - Hyung Seok Kim; Carlos Ornelas; Kailash Chandrashekar; Dan Shi; Pin-en Su; Paolo Madoglio; Yee William Li; Ashoke Ravi (IEEE J. Solid State Circuits, 2013)

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. - Somnath Paul; Turbo Majumder; Charles Augustine; Andres F. Malavasi; S. Usirikayala; Raghavan Kumar; Jisna Kollikunnel; S. Chhabra; Satish Yada; M. L. Barajas; Carlos Ornelas; Dan Lake; et al. (VLSI Circuits, 2020)