Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. - James W. Tschanz; Nam-Sung Kim; Saurabh Dighe; Jason Howard; Gregory Ruhl; Sriram R. Vangal; Siva G. Narendra; Yatin Hoskote; Howard Wilson; Carol Lam; Matthew Shuman; Carlos Tokunaga; et al. (ISSCC, 2007)

Timing yield enhancement through soft edge flip-flop based design. - Michael Wieckowski; Young Min Park; Carlos Tokunaga; Dong Woon Kim; Zhiyoong Foo; Dennis Sylvester; David T. Blaauw (CICC, 2008)

Low-voltage circuit design for widespread sensing applications. - Yu-Shiang Lin; Scott Hanson; Fabio Albano; Carlos Tokunaga; Razi-Ul Haque; Kensall D. Wise; Ann Marie Sastry; David T. Blaauw; Dennis Sylvester (ISCAS, 2008)

Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance. - David T. Blaauw; Sudherssen Kalaiselvan; Kevin Lai; Wei-Hsiang Ma; Sanjay Pant; Carlos Tokunaga; Shidhartha Das; David M. Bull (ISSCC, 2008)

True Random Number Generator With a Metastability-Based Quality Control. - Carlos Tokunaga; David T. Blaauw; Trevor N. Mudge (IEEE J. Solid State Circuits, 2008)

Secure AES engine with a local switched-capacitor current equalizer. - Carlos Tokunaga; David T. Blaauw (ISSCC, 2009)

RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance. - Shidhartha Das; Carlos Tokunaga; Sanjay Pant; Wei-Hsiang Ma; Sudherssen Kalaiselvan; Kevin Lai; David M. Bull; David T. Blaauw (IEEE J. Solid State Circuits, 2009)

Resilient design in scaled CMOS for energy efficiency. - James W. Tschanz; Keith A. Bowman; Muhammad M. Khellah; Chris Wilkerson; Bibiche M. Geuskens; Dinesh Somasekhar; Arijit Raychowdhury; Jaydeep Kulkarni; Carlos Tokunaga; Shih-Lien Lu; Tanay Karnik; Vivek De (ASP-DAC, 2010)

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. - Keith A. Bowman; Carlos Tokunaga; James W. Tschanz; Arijit Raychowdhury; Muhammad M. Khellah; Bibiche M. Geuskens; Shih-Lien Lu; Paolo A. Aseron; Tanay Karnik; Vivek De (CICC, 2010)

Resilient microprocessor design for high performance & energy efficiency. - Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (ISLPED, 2010)

A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. - James W. Tschanz; Keith A. Bowman; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (ISSCC, 2010)

Securing Encryption Systems With a Switched Capacitor Current Equalizer. - Carlos Tokunaga; David T. Blaauw (IEEE J. Solid State Circuits, 2010)

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. - Arijit Raychowdhury; Jim Tschanz; Keith A. Bowman; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. - Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek K. De (IEEE J. Solid State Circuits, 2011)

All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. - Keith A. Bowman; Carlos Tokunaga; James W. Tschanz; Arijit Raychowdhury; Muhammad M. Khellah; Bibiche M. Geuskens; Shih-Lien Lu; Paolo A. Aseron; Tanay Karnik; Vivek K. De (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS. - Arijit Raychowdhury; Carlos Tokunaga; Willem Marco Beltman; Michael Deisher; James W. Tschanz; Vivek De (CICC, 2012)

Design for test and reliability in ultimate CMOS. - Michael Nicolaidis; Lorena Anghel; Nacer-Eddine Zergainoh; Yervant Zorian; Tanay Karnik; Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Carlos Tokunaga; Arijit Raychowdhury; Muhammad M. Khellah; Jaydeep Kulkarni; et al. (DATE, 2012)

A 22nm dynamically adaptive clock distribution for voltage droop tolerance. - Keith A. Bowman; Carlos Tokunaga; Tanay Karnik; Vivek K. De; Jim Tschanz (VLSIC, 2012)

Adaptive and Resilient Circuits for Dynamic Variation Tolerance. - Keith A. Bowman; Carlos Tokunaga; James W. Tschanz; Tanay Karnik; Vivek K. De (IEEE Des. Test, 2013)

A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance. - Keith A. Bowman; Carlos Tokunaga; Tanay Karnik; Vivek K. De; James W. Tschanz (IEEE J. Solid State Circuits, 2013)

A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS. - Arijit Raychowdhury; Carlos Tokunaga; Willem Marco Beltman; Michael Deisher; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2013)

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. - Carlos Tokunaga; Joseph F. Ryan 002; Charles Augustine; Jaydeep P. Kulkarni; Yi-Chun Shih; Stephen T. Kim; Rinkle Jain; Keith A. Bowman; Arijit Raychowdhury; Muhammad M. Khellah; James W. Tschanz; Vivek De (ISSCC, 2014)

Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS. - Minki Cho; Carlos Tokunaga; Muhammad M. Khellah; James W. Tschanz; Vivek De (CICC, 2015)

8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. - Stephen T. Kim; Yi-Chun Shih; Kaushik Mazumdar; Rinkle Jain; Joseph F. Ryan 002; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (ISSCC, 2015)

4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. - Jaydeep P. Kulkarni; Carlos Tokunaga; Paolo A. Aseron; Trang Nguyen; Charles Augustine; James W. Tschanz; Vivek De (ISSCC, 2015)

A fully integrated charge sharing active decap scheme for power supply noise suppression. - Ahmed M. Ammar; Rafik Guindi; Ethan Shih; Carlos Tokunaga; Jim Tschanz; Muhammad M. Khellah (SoCC, 2015)

8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. - Minki Cho; Stephen T. Kim; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (ISSCC, 2016)

Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core. - Minki Cho; Carlos Tokunaga; Stephen T. Kim; James W. Tschanz; Muhammad M. Khellah; Vivek De (VLSI Circuits, 2016)

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. - Stephen T. Kim; Yi-Chun Shih; Kaushik Mazumdar; Rinkle Jain; Joseph F. Ryan 002; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (IEEE J. Solid State Circuits, 2016)

A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. - Jaydeep P. Kulkarni; Carlos Tokunaga; Paolo A. Aseron; Trang Nguyen; Charles Augustine; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2016)

Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating. - Minki Cho; Stephen T. Kim; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (IEEE J. Solid State Circuits, 2017)

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. - Pascal Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (ISSCC, 2018)

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{ text{MIN}}$ Optimization. - Pascal Andreas Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (IEEE J. Solid State Circuits, 2019)

Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. - Jaydeep P. Kulkarni; Andres Malavasi; Charles Augustine; Carlos Tokunaga; Jim Tschanz; Muhammad M. Khellah; Vivek De (VLSI Circuits, 2020)

CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation. - Brian Crafton; Samuel Spetalnick; Jong-Hyeok Yoon; Wei Wu; Carlos Tokunaga; Vivek De; Arijit Raychowdhury (A-SSCC, 2021)

A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses. - Saurabh Kumar 003; Minki Cho; Luke R. Everson; Andres Malavasi; Dan Lake; Carlos Tokunaga; Muhammad M. Khellah; James W. Tschanz; Vivek De; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Improving compute in-memory ECC reliability with successive correction. - Brian Crafton; Zishen Wan; Samuel Spetalnick; Jong-Hyeok Yoon; Wei Wu; Carlos Tokunaga; Vivek De; Arijit Raychowdhury (DAC, 2022)

Analysis of the Effect of Hot Carrier Injection in An Integrated Inductive Voltage Regulator. - Shida Zhang; Nael Mizanur Rahman; Venkata Chaitanya Krishna Chekuri; Carlos Tokunaga; Saibal Mukhopadhyay (ISLPED, 2022)

An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS. - Gregory K. Chen; Phil C. Knag; Carlos Tokunaga; Ram K. Krishnamurthy (VLSI Technology and Circuits, 2022)

A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS. - Raghavan Kumar; Avinash Varna 001; Carlos Tokunaga; Sachin Taneja; Vivek De; Sanu Mathew (ISSCC, 2023)

An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS. - Gregory K. Chen; Phil C. Knag; Carlos Tokunaga; Ram K. Krishnamurthy (IEEE J. Solid State Circuits, 2023)

Measurement of Aging Effect in a Digitally Controlled Inductive Voltage Regulator in 65nm. - Shida Zhang; Nael Mizanur Rahman; Wei Chun Wang; Narasimha Vasishta Kidambi; Carlos Tokunaga; Saibal Mukhopadhyay (IRPS, 2024)

A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS. - Raghavan Kumar; Avinash L. Varna; Carlos Tokunaga; Sachin Taneja; Vivek De; Sanu K. Mathew (IEEE J. Solid State Circuits, 2024)

A Comparative Analysis of Aging Effects on Computing-in-Memory Systems in 28nm CMOS. - Shida Zhang; Wei-Chun Wang; Carlos Tokunaga; Saibal Mukhopadhyay (IRPS, 2025)

8.7 A Dual VDD-Temperature Sensor Employing Sensor Fusion with 2.4°C, 9mV (±3σ) Inaccuracy in 65nm CMOS. - Hikmet Seha Ozturk; Julian Arenas; Carlos Tokunaga; Nasser A. Kurd; Visvesh Sathe 001 (ISSCC, 2025)