A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck. - Claudio Brunelli; Fabio Garzia; Carmelo Giliberto; Jari Nurmi (FPL, 2008)

Implementation of W-CDMA slot synchronization on a reconfigurable System-on-Chip. - Fabio Garzia; Claudio Brunelli; Carmelo Giliberto; Roberto Airoldi; Jari Nurmi (SoC, 2008)

Mapping of the FFT on a reconfigurable architecture targeted to SDR applications. - Fabio Garzia; Roberto Airoldi; Jari Nurmi; Carmelo Giliberto; Claudio Brunelli (SoC, 2009)