Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core. - Jens E. Becker; Carsten Bieser; Alexander Thomas; Klaus D. Müller-Glaser; Jürgen Becker 001 (MSE, 2003)

Hardware/Software Co-Training Lab: From VHDL Bit-Level Coding up to CASE-Tool Based System Modeling. - Carsten Bieser; Klaus D. Müller-Glaser; Jürgen Becker 001 (MSE, 2005)

COMPASS - A Novel Concept of a Reconfigurable Platform for Automotive System Development and Test. - Carsten Bieser; Klaus D. Müller-Glaser (IEEE International Workshop on Rapid System Prototyping, 2005)

A Novel FPGA Design Acceleration Methodology Supported by a Unique RP Platform for Fast and Easy System Develpoment. - Carsten Bieser (FPL, 2006)

A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System Setup. - Carsten Bieser; Martin Bahlinger; Matthias Heinz; Christian Stops; Klaus D. Müller-Glaser (FPL, 2006)

Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs. - Carsten Bieser; Klaus D. Müller-Glaser (IEEE International Workshop on Rapid System Prototyping, 2006)

Konzept einer bibliotheksbasiert konfigurierbaren Hardware-Testeinrichtung für eingebettete elektronische Systeme. - Carsten Bieser (Engelhardt und Bauer, 2007)