Dynamic Processor Reconfiguration. - Michael Hübner 001; Carsten Tradowsky; Diana Göhringer; Lars Braun; Florian Thoma; Jörg Henkel; Jürgen Becker 001 (ReConFig, 2011)

On Dynamic Run-time Processor Pipeline Reconfiguration. - Carsten Tradowsky; Florian Thoma; Michael Hübner 001; Jürgen Becker 001 (IPDPS Workshops, 2012)

Determination of on-chip temperature gradients on reconfigurable hardware. - Carsten Tradowsky; Enrique Cordero; Thorsten Deuser; Michael Hübner 001; Jürgen Becker 001 (ReConFig, 2012)

Adaptive processor architecture - invited paper. - Michael Hübner 001; Diana Göhringer; Carsten Tradowsky; Jörg Henkel; Jürgen Becker 001 (ICSAMOS, 2012)

LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture. - Carsten Tradowsky; Florian Thoma; Michael Hübner 001; Jürgen Becker 001 (SIES, 2012)

ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores. - Peter Figuli; Carsten Tradowsky; Nadine Gaertner; Jürgen Becker 001 (ISSoC, 2013)

LImbiC: An adaptable architecture description language model for developing an application-specific image processor. - Carsten Tradowsky; Tanja Harbaum; Shaver Deyerle; Jürgen Becker 001 (ISVLSI, 2013)

Towards Dynamic Cache and Bandwidth Invasion. - Carsten Tradowsky; Martin Schreiber 001; Malte Vesper; Ivan Domladovec; Maximilian Braun; Hans-Joachim Bungartz; Jürgen Becker 001 (ARC, 2014)

SmartLoCore: A Concept for an Adaptive Power-Aware Localization Processor. - Carsten Tradowsky; Tobias Gädeke; Thomas Bruckschlögl; Wilhelm Stork; Klaus D. Müller-Glaser; Jürgen Becker 001 (PDP, 2014)

A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware. - Peter Figuli; Carsten Tradowsky; Jose Martinez; Harry Sidiropoulos; Kostas Siozios; Holger Stenschke; Dimitrios Soudris; Jürgen Becker 001 (ARC, 2015)

TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools. - Kostas Siozios; Peter Figuli; Harry Sidiropoulos; Carsten Tradowsky; Dionysios Diamantopoulos; Konstantinos Maragos 001; Shalina Percy Delicia; Dimitrios Soudris; Jürgen Becker 001 (ARC, 2015)

A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems. - Carsten Tradowsky; Enrique Cordero; Christoph Orsinger; Malte Vesper; Jürgen Becker 001 (ARC, 2016)

Adaptive Cache Structures. - Carsten Tradowsky; Enrique Cordero; Christoph Orsinger; Malte Vesper; Jürgen Becker 001 (ARCS, 2016)

Methoden zur applikationsspezifischen Effizienzsteigerung adaptiver Prozessorplattformen. - Carsten Tradowsky (2016)

Pegasus: Efficient data transfers for PGAS languages on non-cache-coherent many-cores. - Manuel Mohr; Carsten Tradowsky (DATE, 2017)

Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration. - Tanja Harbaum; Christoph Schade; Marvin Damschen; Carsten Tradowsky; Lars Bauer; Jörg Henkel; Jürgen Becker 001 (SoCC, 2017)