A process algebra interpretation of a verification oriented overlanguage of VHDL. - Catherine Bayol; Bernard Soulas; Dominique Borrione; Fulvio Corno; Paolo Prinetto (EURO-DAC, 1994)

System-Level Modeling and Verification: a Comprehensive Design Methodology. - Paolo Camurati; Fulvio Corno; Paolo Prinetto; Catherine Bayol; Bernard Soulas (EDAC-ETC-EUROASIC, 1994)

Une approche structurelle et comportementale de modélisation pour la vérification de composants VLSI. (A structural and Behavioral Modeling Approach for the Verification of VLSI Components). - Catherine Bayol (1995)