Ce Yang
Orcid: 0000-0002-4850-4094Affiliations:
- d-Matrix, Santa Clara, CA, USA
- University of Southern California, Los Angeles, CA, USA
According to our database1,
Ce Yang
authored at least 7 papers
between 2021 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
11.2 A Blocker-Tolerant Receiver with VCO-Based Non-Uniform Multi-Level Time-Approximation Filter with -36dB EVM in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
26.1: A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and -30.8dB EVM in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
A Blocker-Tolerant Non-Uniform Sub-Sampling Receiver With a Non-Uniform Discrete-Time FIR Filter.
IEEE J. Solid State Circuits, December, 2024
5.3 A 0.072mm<sup>2</sup> 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE J. Solid State Circuits, May, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2021
26.6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021