FPGA-based digital direct-conversion transceiver for Nuclear Magnetic Resonance Systems. - Cecil Accetti R. de A. Melo; Ricardo E. de Souza (SBCCI, 2012)

Oolong: A Baseband processor extension to the RISC-V ISA. - Cecil Accetti R. de A. Melo; Edna Barros (ASAP, 2016)

A 42fps full-HD ORB feature extraction accelerator with reduced memory overhead. - Rongdi Sun; Peilin Liu; Jun Wang 137; Cecil Accetti; Abid A. Naqvi (FPT, 2017)

A 974GOPS/W Multi-level Parallel Architecture for Binary Weight Network Acceleration. - Rongdi Sun; Peilin Liu; Cecil Accetti; Abid A. Naqvi; Haroon Ahmed; Jiuchao Qian (ISCAS, 2018)

An FPGA-Based RFID Baseband Processor Using a RISC-V Platform. - Pedro J. A. Ishimaru; Antonyus P. A. Ferreira; Vanessa O. Ogg; Cecil Accetti R. de A. Melo; Edna Natividade da Silva Barros (SBCCI, 2018)

A Platform for Full-Stack Functional Programming. - Cecil Accetti R. de A. Melo; Peilin Liu; Rendong Ying (ISCAS, 2020)

Architectural Support for Functional Programming. - Cecil Accetti; Peilin Liu (VLSI-SoC, 2022)

Structured Combinators for Efficient Graph Reduction. - Cecil Accetti; Rendong Ying; Peilin Liu (IEEE Comput. Archit. Lett., 2022)