Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter. - Cécile Braunstein; Emmanuelle Encrenaz (IEEE International Workshop on Rapid System Prototyping, 2006)

Using CTL formulae as component abstraction in a design and verification flow. - Cécile Braunstein; Emmanuelle Encrenaz (ACSD, 2007)

CTL-property Transformations along an Incremental Design Process. - Cécile Braunstein; Emmanuelle Encrenaz (Int. J. Softw. Tools Technol. Transf., 2007)

Complementary Formal Approaches for Dependability Analysis. - Souheib Baarir; Cécile Braunstein; Renaud Clavel; Emmanuelle Encrenaz; Jean-Michel Ilié; Régis Leveugle; Isabelle Mounier; Laurence Pierre; Denis Poitrenaud (DFT, 2009)

Increasing the Accuracy of SAT-based Debugging. - André Sülflow; Görschwin Fey; Cécile Braunstein; Ulrich Kühne; Rolf Drechsler (MBMV, 2009)

Feasibility analysis for robustness quantification by symbolic model checking. - Souheib Baarir; Cécile Braunstein; Emmanuelle Encrenaz; Jean-Michel Ilié; Isabelle Mounier; Denis Poitrenaud; Sana Younès (Formal Methods Syst. Des., 2011)

An efficient refinement strategy exploiting component properties in a cegar process. - Syed Hussein Syed Alwi; Cécile Braunstein; Emmanuelle Encrenaz (FDL, 2012)

Efficient Refinement Strategy Exploiting Component Properties in a CEGAR Process. - Syed Hussein Syed Alwi; Cécile Braunstein; Emmanuelle Encrenaz (FDL (Selected Papers), 2012)

Complete Model-Based Equivalence Class Testing for the ETCS Ceiling Speed Monitor. - Cécile Braunstein; Anne E. Haxthausen; Wen-ling Huang; Felix Hübner 001; Jan Peleska 001; Uwe Schulze; Linh Vu Hong (ICFEM, 2014)