CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults. - Cecilia Metra; Michele Favalli; Piero Olivo; Bruno Riccò (ITC, 1992)

Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block. - Cecilia Metra; Michele Favalli; Piero Olivo; Bruno Riccò (DFT, 1993)

A Highly Testable 1-out-of-3 CMOS Checker. - Cecilia Metra; Michele Favalli; Piero Olivo; Bruno Riccò (DFT, 1993)

CMOS Self Checking Circuits with Faulty Sequential Functional Block. - Cecilia Metra; Michele Favalli; Bruno Riccò (DFT, 1994)

Highly Testable and Compact 1-out-of-n CMOS Checkers. - Cecilia Metra; Michele Favalli; Bruno Riccò (DFT, 1994)

Novel Berger code checker. - Cecilia Metra; Michele Favalli; Bruno Riccò (DFT, 1995)

Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults. - Cecilia Metra; Michele Favalli; Piero Olivo; Bruno Riccò (J. Electron. Test., 1995)

Compact and Highly Testable Error Indicator for Self-Checking Circuits. - Cecilia Metra; Michele Favalli; Bruno Riccò (DFT, 1996)

Tree Checkers for Applications with Low Power-Delay Requirements. - Cecilia Metra; Michele Favalli; Bruno Riccò (DFT, 1996)

Embedded two-rail checkers with on-line testing ability. - Cecilia Metra; Michele Favalli; Bruno Riccò (VTS, 1996)

Sensing circuit for on-line detection of delay faults. - Michele Favalli; Cecilia Metra (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Testing scheme for IC's clocks. - Michele Favalli; Cecilia Metra (ED&TC, 1997)

Low-level error recovery mechanism for self-checking sequential circuits. - Michele Favalli; Cecilia Metra (DFT, 1997)

Fast and area-time efficient Berger code checkers. - Yu-Yau Guo; Jien-Chung Lo; Cecilia Metra (DFT, 1997)

Compact and low power on-line self-testing voting scheme. - Cecilia Metra; Michele Favalli; Bruno Riccò (DFT, 1997)

On-Line Testing Scheme for Clock's Faults. - Cecilia Metra; Michele Favalli; Bruno Riccò (ITC, 1997)

Highly testable and compact single output comparator. - Cecilia Metra; Michele Favalli; Bruno Riccò (VTS, 1997)

On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits. - Cecilia Metra; Michele Favalli; Piero Olivo; Bruno Riccò (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Highly Testable and Compact 1-out-of-n Code Checker with Single Output. - Cecilia Metra; Michele Favalli; Bruno Riccò (DATE, 1998)

Novel Technique for Testing FPGAs. - Cecilia Metra; Michel Renovell; Giovanni A. Mojoli; Jean-Michel Portal; Sandro Pastore; Joan Figueras; Yervant Zorian; Davide Salvi; Giacomo R. Sechi (DATE, 1998)

Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems. - Sergio D'Angelo; Cecilia Metra; Sandro Pastore; A. Pogutz; Giacomo R. Sechi (DFT, 1998)

Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks. - Cecilia Metra; Michele Favalli; Bruno Riccò (DFT, 1998)

On-line detection of logic errors due to crosstalk, delay, and transient faults. - Cecilia Metra; Michele Favalli; Bruno Riccò (ITC, 1998)

Concurrent Checking of Clock Signal Correctness. - Cecilia Metra; Michele Favalli; Bruno Riccò (IEEE Des. Test Comput., 1998)

On the Design of Self-Checking Functional Units Based on Shannon Circuits. - Michele Favalli; Cecilia Metra (DATE, 1999)

Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems. - Sergio D'Angelo; Giacomo R. Sechi; Cecilia Metra (DFT, 1999)

Self-checking scheme for very fast clocks' skew correction. - Cecilia Metra; Flavio Giovanelli; Mani Soma; Bruno Riccò (ITC, 1999)

Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing. - Michele Favalli; Cecilia Metra (IEEE Trans. Very Large Scale Integr. Syst., 1999)

On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values. - Cecilia Metra; Michele Favalli; Bruno Riccò (DATE, 2000)

Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs. - Monica Alderighi; Sergio D'Angelo; Giacomo R. Sechi; Cecilia Metra (DFT, 2000)

Bridging Faults in Pipelined Circuits. - Michele Favalli; Cecilia Metra (J. Electron. Test., 2000)

Intermediacy Prediction for High Speed Berger Code Checkers. - Cecilia Metra; Jien-Chung Lo (J. Electron. Test., 2000)

Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines. - Cecilia Metra; Michele Favalli; Bruno Riccò (IEEE Trans. Computers, 2000)

Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits. - Cecilia Metra; Michele Favalli; Bruno Riccò (VLSI Design, 2000)

Optimization of error detecting codes for the detection of crosstalk originated errors. - Michele Favalli; Cecilia Metra (DATE, 2001)

Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. - Cecilia Metra; Stefano Di Francescantonio; Bruno Riccò; T. M. Mak (DFT, 2001)

Novel Fault-Tolerant Adder Design for FPGA-Based Systems. - Monica Alderighi; Sergio D'Angelo; Giacomo R. Sechi; Cecilia Metra (IOLTW, 2001)

On-line testing of transient and crosstalk faults affecting interconnections of FPGA-implemented systems. - Cecilia Metra; Andrea Pagano; Bruno Riccò (ITC, 2001)

Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems. - Fabrizio Lombardi; Cecilia Metra (IEEE Des. Test Comput., 2001)

Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths. - Michele Favalli; Cecilia Metra (DATE, 2002)

Self-Checking Scheme for the On-Line Testing of Power Supply Noise. - Cecilia Metra; Luca Schiano; Bruno Riccò; Michele Favalli (DATE, 2002)

On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits. - Cecilia Metra; Stefano Di Francescantonio; Giuseppe Marrale (DFT, 2002)

Coding Scheme for Low Energy Consumption Fault-Tolerant Bus. - Daniele Rossi 001; Steven V. E. S. van Dijk; Richard P. Kleihorst; A. H. Nieuwland; Cecilia Metra (IOLTW, 2002)

Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. - Cecilia Metra; Stefano Di Francescantonio; T. M. Mak (ITC, 2002)

Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. - Daniele Rossi 001; Cecilia Metra; Bruno Riccò (MTDT, 2002)

Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. - Luca Schiano; Cecilia Metra; Diego Marino (MTDT, 2002)

Online Testing Approach for Very Deep-Submicron ICs. - Michele Favalli; Cecilia Metra (IEEE Des. Test Comput., 2002)

Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. - Michele Favalli; Cecilia Metra (J. Electron. Test., 2002)

On-Chip Clock Faults' Detector. - Cecilia Metra; Michele Favalli; Stefano Di Francescantonio; Bruno Riccò (J. Electron. Test., 2002)

Guest Editorial. - Dimitris Nikolos; John P. Hayes; Michael Nicolaidis; Cecilia Metra (J. Electron. Test., 2002)

High Speed and Highly Testable Parallel Two-Rail Code Checker. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (DATE, 2003)

Automatic Modification of Sequential Circuits for Self-Checking Implementation. - Cecilia Metra; Stefano Di Francescantonio; Martin Omaña 001 (DFT, 2003)

Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. - Cecilia Metra; T. M. Mak; Daniele Rossi 001 (DFT, 2003)

Error Correcting Codes for Crosstalk Effect Minimization. - Daniele Rossi 001; S. Cavallotti; Cecilia Metra (DFT, 2003)

A Model for Transient Fault Propagation in Combinatorial Logic. - Martin Omaña 001; Giacinto Papasso; Daniele Rossi 001; Cecilia Metra (IOLTS, 2003)

Power Consumption of Fault Tolerant Codes: the Active Elements. - Daniele Rossi 001; Steven V. E. S. van Dijk; Richard P. Kleihorst; André K. Nieuwland; Cecilia Metra (IOLTS, 2003)

Crosstalk Effect Minimization for Encoded Busses. - L. Di Silvio; Daniele Rossi 001; Cecilia Metra (IOLTS, 2003)

Novel Transient Fault Hardened Static Latch. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (ITC, 2003)

Guest Editorial. - Cecilia Metra; Matteo Sonza Reorda (J. Electron. Test., 2003)

Error Correcting Strategy for High Speed and High Density Reliable Flash Memories. - Daniele Rossi 001; Cecilia Metra (J. Electron. Test., 2003)

Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults. - Cecilia Metra; Stefano Di Francescantonio; Michele Favalli; Bruno Riccò (Microelectron. J., 2003)

Self-checking design, implementation, and measurement of a controller for track-side railway systems. - Luca Schiano; Cecilia Metra; Diego Marino (IEEE Trans. Instrum. Meas., 2003)

Concurrent detection of power supply noise. - Cecilia Metra; Luca Schiano; Michele Favalli (IEEE Trans. Reliab., 2003)

Fault secureness need for next generation high performance microprocessor design for testability structures. - Cecilia Metra; T. M. Mak; Martin Omaña 001 (Conf. Computing Frontiers, 2004)

Are Our Design for Testability Features Fault Secure? - Cecilia Metra; T. M. Mak; Martin Omaña 001 (DATE, 2004)

Fast and Low-Cost Clock Deskew Buffer. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (DFT, 2004)

Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop. - José Manuel Cazeaux; Martin Omaña 001; Cecilia Metra (IOLTS, 2004)

New High Speed CMOS Self-Checking Voter. - José Manuel Cazeaux; Daniele Rossi 001; Cecilia Metra (IOLTS, 2004)

Hardware Reconfiguration Scheme for High Availability Systems. - Cecilia Metra; A. Ferrari; Martin Omaña 001; Andrea Pagni (IOLTS, 2004)

Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems. - Daniele Rossi 001; A. Muccio; André K. Nieuwland; Atul Katoch; Cecilia Metra (IOLTS, 2004)

Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. - Cecilia Metra; T. M. Mak; Martin Omaña 001 (ITC, 2004)

Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates. - André Ivanov; Fabrizio Lombardi; Cecilia Metra (IEEE Des. Test Comput., 2004)

Model for Transient Fault Susceptibility of Combinational Circuits. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (J. Electron. Test., 2004)

Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. - Cecilia Metra; Stefano Di Francescantonio; T. M. Mak (IEEE Trans. Computers, 2004)

TMR voting in the presence of crosstalk faults at the voter inputs. - Michele Favalli; Cecilia Metra (IEEE Trans. Reliab., 2004)

The Other Side of the Timing Equation: a Result of Clock Faults. - Cecilia Metra; Martin Omaña 001; Daniele Rossi 001; José Manuel Cazeaux; T. M. Mak (DFT, 2005)

Multiple Transient Faults in Logic: An Issue for Next Generation ICs. - Daniele Rossi 001; Martin Omaña 001; Fabio Toma; Cecilia Metra (DFT, 2005)

On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. - José Manuel Cazeaux; Daniele Rossi 001; Martin Omaña 001; Cecilia Metra; Abhijit Chatterjee (IOLTS, 2005)

Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. - Yuvraj Singh Dhillon; Abdulkadir Utku Diril; Abhijit Chatterjee; Cecilia Metra (IOLTS, 2005)

Coding Techniques for Low Switching Noise in Fault Tolerant Busses. - André K. Nieuwland; Atul Katoch; Daniele Rossi 001; Cecilia Metra (IOLTS, 2005)

On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization. - Martin Omaña 001; O. Losco; Cecilia Metra; Andrea Pagni (IOLTS, 2005)

Low Cost Scheme for On-Line Clock Skew Compensation. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (VTS, 2005)

Exploiting ECC Redundancy to Minimize Crosstalk Impact. - Daniele Rossi 001; André K. Nieuwland; Atul Katoch; Cecilia Metra (IEEE Des. Test Comput., 2005)

New ECC for Crosstalk Impact Minimization. - Daniele Rossi 001; André K. Nieuwland; Atul Katoch; Cecilia Metra (IEEE Des. Test Comput., 2005)

Self-Checking Voter for High Speed TMR Systems. - José Manuel Cazeaux; Daniele Rossi 001; Cecilia Metra (J. Electron. Test., 2005)

Low Cost and High Speed Embedded Two-Rail Code Checker. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (IEEE Trans. Computers, 2005)

Novel on-chip circuit for jitter testing in high-speed PLLs. - José Manuel Cazeaux; Martin Omaña 001; Cecilia Metra (IEEE Trans. Instrum. Meas., 2005)

Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. - Martin Omaña 001; José Manuel Cazeaux; Daniele Rossi 001; Cecilia Metra (DATE, 2006)

Analysis of the impact of bus implemented EDCs on on-chip SSN. - Daniele Rossi 001; Carlo Steiner; Cecilia Metra (DATE, 2006)

Can Clock Faults be Detected Through Functional Test? - Cecilia Metra; Daniele Rossi 001; Martin Omaña 001; José Manuel Cazeaux; T. M. Mak (DDECS, 2006)

Testing Reversible 1D Arrays for Molecular QCA. - Xiaojun Ma; Jing Huang 001; Cecilia Metra; Fabrizio Lombardi (DFT, 2006)

Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. - Cecilia Metra; Martin Omaña 001; Daniele Rossi 001; José Manuel Cazeaux; T. M. Mak (IOLTS, 2006)

Checker No-Harm Alarm Robustness. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra; Andrea Pagni (IOLTS, 2006)

Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC). - Jien-Chung Lo; Cecilia Metra; Fabrizio Lombardi (IEEE Trans. Computers, 2006)

Interactive presentation: Pulse propagation for the detection of small delay defects. - Michele Favalli; Cecilia Metra (DATE, 2007)

Testing Reversible One-Dimensional QCA Arrays for Multiple Faults. - Jing Huang 001; Xiaojun Ma; Cecilia Metra; Fabrizio Lombardi (DFT, 2007)

Configurable Error Control Scheme for NoC Signal Integrity. - Daniele Rossi 001; Paolo Angelini; Cecilia Metra (IOLTS, 2007)

Novel compensation scheme for local clocks of high performance microprocessors. - Cecilia Metra; Martin Omaña 001; T. M. Mak; Simon Tam 001 (ITC, 2007)

Novel Approach to Clock Fault Testing for High Performance Microprocessors. - Cecilia Metra; Martin Omaña 001; T. M. Mak; Simon Tam 001 (VTS, 2007)

Guest Editors' Introduction: The State of the Art in Nanoscale CAD. - Fabrizio Lombardi; Cecilia Metra (IEEE Des. Test Comput., 2007)

Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. - Cecilia Metra; Daniele Rossi 001; T. M. Mak (IEEE Trans. Computers, 2007)

Latch Susceptibility to Transient Faults and New Hardening Approach. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (IEEE Trans. Computers, 2007)

Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. - Cecilia Metra; Martin Omaña 001; T. M. Mak; Asifur Rahman; Simon Tam 001 (DFT, 2008)

Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. - Cecilia Metra; Daniele Rossi 001; Martin Omaña 001; Abhijit Jas; Rajesh Galivanche (ETS, 2008)

Risks for Signal Integrity in System in Package and Possible Remedies. - Daniele Rossi 001; Paolo Angelini; Cecilia Metra; Giovanni Campardo; Gian Pietro Vanalli (ETS, 2008)

Simultaneous Switching Noise: The Relation between Bus Layout and Coding. - Daniele Rossi 001; André K. Nieuwland; Cecilia Metra (IEEE Des. Test Comput., 2008)

Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA. - Xiaojun Ma; Jing Huang 001; Cecilia Metra; Fabrizio Lombardi (J. Electron. Test., 2008)

Checkers' No-Harm Alarms and Design Approaches to Tolerate Them. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra (J. Electron. Test., 2008)

Power Consumption of Fault Tolerant Busses. - Daniele Rossi 001; André K. Nieuwland; Steven V. E. S. van Dijk; Richard P. Kleihorst; Cecilia Metra (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors. - Martin Omaña 001; Marcin Marzencki; Roberto Specchia; Cecilia Metra; Bozena Kaminska (DFT, 2009)

Novel High Speed Robust Latch. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (DFT, 2009)

Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates. - Xiaojun Ma; Jing Huang 001; Cecilia Metra; Fabrizio Lombardi (J. Electron. Test., 2009)

Testing Resistive Opens and Bridging Faults Through Pulse Propagation. - Michele Favalli; Cecilia Metra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Accurate Linear Model for SET Critical Charge Estimation. - Daniele Rossi 001; José Manuel Cazeaux; Martin Omaña 001; Cecilia Metra; Abhijit Chatterjee (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Novel low-cost aging sensor. - Martin Omaña 001; Daniele Rossi 001; Nicolò Bosio; Cecilia Metra (Conf. Computing Frontiers, 2010)

Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. - Daniele Rossi 001; Martin Omaña 001; Gianluca Berghella; Cecilia Metra; Abhijit Jas; Chandra Tirumurti; Rajesh Galivanche (Conf. Computing Frontiers, 2010)

On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter. - Martin Omaña 001; Daniele Giaffreda; Cecilia Metra; T. M. Mak; Simon Tam 001; Asifur Rahman (DFT, 2010)

Transient Fault and Soft Error On-die Monitoring Scheme. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra (DFT, 2010)

Secure communication protocol for wireless sensor networks. - Daniele Rossi 001; Martin Omaña 001; Daniele Giaffreda; Cecilia Metra (EWDTS, 2010)

High-Performance Robust Latches. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (IEEE Trans. Computers, 2010)

Error correcting code analysis for cache memory high reliability and performance. - Daniele Rossi 001; N. Timoncini; M. Spica; Cecilia Metra (DATE, 2011)

Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition. - Daniele Giaffreda; Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (DFT, 2011)

Impact of Aging Phenomena on Soft Error Susceptibility. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra; Alessandro Paccagnella (DFT, 2011)

Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems. - Cecilia Metra; Rajesh Galivanche (IEEE Trans. Computers, 2011)

Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors. - Martin Omaña 001; Cecilia Metra; T. M. Mak; Simon Tam 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. - Cristiana Bolchini; Antonio Miele; Chiara Sandionigi; Marco Ottavi; Salvatore Pontarelli; Adelio Salsano; Cecilia Metra; Martin Omaña 001; Daniele Rossi 001; Matteo Sonza Reorda; Luca Sterpone; Massimo Violante; et al. (DFT, 2012)

Faults affecting the control blocks of PV arrays and techniques for their concurrent detection. - Martin Omaña 001; Daniele Rossi 001; G. Collepalumbo; Cecilia Metra; Fabrizio Lombardi (DFT, 2012)

New Design for Testability Approach for Clock Fault Testing. - Cecilia Metra; Martin Omaña 001; T. M. Mak; Simon Tam 001 (IEEE Trans. Computers, 2012)

Novel approach to reduce power droop during scan-based logic BIST. - Martin Omaña 001; Daniele Rossi 001; Filippo Fuzzi; Cecilia Metra; Chandra Tirumurti; R. Galivache (ETS, 2013)

Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder. - Daniele Rossi 001; Martin Omaña 001; G. Garrammone; Cecilia Metra; Abhijit Jas; Rajesh Galivanche (J. Electron. Test., 2013)

Low Cost NBTI Degradation Detection and Masking Approaches. - Martin Omaña 001; Daniele Rossi 001; Nicolò Bosio; Cecilia Metra (IEEE Trans. Computers, 2013)

Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection. - Martin Omaña 001; Daniele Rossi 001; Daniele Giaffreda; Roberto Specchia; Cecilia Metra; Marcin Marzencki; Bozena Kaminska (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Power droop reduction during Launch-On-Shift scan-based logic BIST. - Martin Omaña 001; Daniele Rossi 001; Edda Beniamino; Cecilia Metra; Chandra Tirumurti; Rajesh Galivanche (DFT, 2014)

Clock Faults Induced Min and Max Delay Violations. - Daniele Rossi 001; Martin Omaña 001; José Manuel Cazeaux; Cecilia Metra; T. M. Mak (J. Electron. Test., 2014)

Intermittent and Transient Fault Diagnosis on Sparse Code Signatures. - Michael A. Kochte; Atefe Dalirsani; Andrea Bernabei; Martin Omaña 001; Cecilia Metra; Hans-Joachim Wunderlich (ATS, 2015)

Low-Cost On-Chip Clock Jitter Measurement Scheme. - Martin Omaña 001; Daniele Rossi 001; Daniele Giaffreda; Cecilia Metra; T. M. Mak; Asifur Rahman; Simon Tam 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Modeling and Detection of Hotspot in Shaded Photovoltaic Cells. - Daniele Rossi 001; Martin Omaña 001; Daniele Giaffreda; Cecilia Metra (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Impact of Bias Temperature Instability on Soft Error Susceptibility. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra; Alessandro Paccagnella (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Inverters' self-checking monitors for reliable photovoltaic systems. - Martin Omaña 001; A. Fiore; Cecilia Metra (DATE, 2016)

Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST. - Martin Omaña 001; Daniele Rossi 001; Edda Beniamino; Cecilia Metra; Chandrasekharan Tirumurti; Rajesh Galivanche (IEEE Trans. Computers, 2016)

New Approaches for Power Binning of High Performance Microprocessors. - Martin Omaña 001; Marco Padovani; Kreshnik Veliu; Cecilia Metra; Juergen Alt; Rajesh Galivanche (IEEE Trans. Computers, 2017)

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. - Martin Omaña 001; Daniele Rossi 001; Filippo Fuzzi; Cecilia Metra; Chandra Tirumurti; Rajesh Galivanche (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Low-Cost Strategy to Mitigate the Impact of Aging on Latches' Robustness. - Martin Omaña 001; TusharaSandeep Edara; Cecilia Metra (IEEE Trans. Emerg. Top. Comput., 2018)

The 2019 IEEE Computer Society: Targeting Member Satisfaction and Technical Excellence. - Cecilia Metra (Computer, 2019)

The 2019 IEEE Computer Society: Hit Target on Member Satisfaction and Technical Excellence. - Cecilia Metra (Computer, 2019)

Low-Cost Strategy for Bus Propagation Delay Reduction. - Martin Omaña 001; S. Govindaraj; Cecilia Metra (J. Electron. Test., 2019)

Special Section on Emerging Trends and Design Paradigms for Memory Systems and Storage. - Rob Aitken; Cecilia Metra (IEEE Trans. Emerg. Top. Comput., 2019)

Message from the Editor-in-Chief. - Cecilia Metra (IEEE Trans. Emerg. Top. Comput., 2019)

Fault-Tolerant Inverters for Reliable Photovoltaic Systems. - Martin Omaña 001; Alessandro Fiore; Marco Mongitore; Cecilia Metra (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Guest Editor's Introduction: Special Section on High Dependability Systems. - Cecilia Metra; Matteo Sonza Reorda (IEEE Trans. Emerg. Top. Comput., 2020)

Novel BTI Robust Ring-Oscillator-Based Physically Unclonable Function. - Marco Grossi; Martin Omaña 001; Daniele Rossi 001; Biagio Marzulli; Cecilia Metra (IOLTS, 2022)

Impact of Soft Errors on High Performance Autoencoders for Cyberattack Detection. - Fabrizio Finelli; Martin Omaña 001; Cecilia Metra (LATS, 2022)

Reliability Risks Due to Faults Affecting Selectors of ReRAMs and Possible Solutions. - Martin Omaña 001; Sejuti Bardhan; Cecilia Metra (IEEE Trans. Emerg. Top. Comput., 2022)

RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters. - William Fornaciari; Federico Reghenzani; Federico Terraneo; Davide Baroffio; Cecilia Metra; Martin Omaña 001; Josie E. Rodriguez Condia; Matteo Sonza Reorda; Robert Birke; Iacopo Colonnelli; Gianluca Mittone; Marco Aldinucci; et al. (SAMOS, 2023)

A PCI Express Based Data Acquisition System for the Monitoring of Code Traces of RISC-V Microprocessors. - Marco Grossi; Simone Manoni; Emanuele Parisi; Martin Omaña 001; Cecilia Metra; Fabrizio Alfonsi; Alessandro Gabrielli; Andrea Acquaviva (ICSRS, 2024)

Silent Data Corruption and Reliability Risks due to Faults Affecting High Performance Microprocessors' Caches. - Martin Omaña 001; A. Manfredi; Cecilia Metra; R. Locatelli; M. Chiavacci; S. Petrucci (IOLTS, 2024)

Reliability of AI in Predicting the State of Health of Li-Ion Batteries*. - Sara Cretí; Martin Omaña 001; Cecilia Metra; Gianni Borelli (IOLTS, 2024)

On the Reliability of Clock Monitoring Units for Safety Critical Applications' Microcontrollers. - M. Zhupa; M. Naldi; Maira Omaña; Cecilia Metra (IOLTS, 2024)

On-Line Test of Fully Integrated Voltage Regulators for High Performance Microprocessors of Autonomous Systems. - Martin Omaña 001; A. Menghi; A. Stefani; E. Vicini; Cecilia Metra; G. Froio; S. Petrucci (IOLTS, 2025)

Novel Physical Unclonable Function Implementation for Microcontrollers and Field Programmable Gate Arrays. - Marco Grossi; Martin Omaña 001; Cecilia Metra; Andrea Acquaviva (IEEE Access, 2025)

The Emerging Metaverse: IEEE ISEMV 2024 Retrospective and Future Directions. - Louis Nisiotis; Cecilia Metra; Jyotika Athavale; Dejan S. Milojicic; Stephen Dukes; Jeewika Ranaweera; Sin-Kuen Hawkins (Computer, 2025)