Building the 4 Processor SB-PRAM Prototype. - Peter Bach; Michael Braun 002; Arno Formella; Jörg Friedrich; Thomas Grün; Cédric Lichtenau (HICSS (5), 1997)

Highly Concurrent Locking in Shared Memory Database Systems. - Christian Jacobi 002; Cédric Lichtenau (Euro-Par, 1999)

Entwurf und Realisierung des Aufbaus und der Testumgebung der SB-PRAM. - Cédric Lichtenau (2000)

Real PRAM Programming. - Wolfgang J. Paul; Peter Bach; Michael Bosch; Jörg Fischer; Cédric Lichtenau; Jochen Röhrig (Euro-Par, 2002)

A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features. - Norman J. Rohrer; Cédric Lichtenau; Peter A. Sandon; Paul Kartschoke; Erwin B. Cohen; Miles G. Canada; Thomas Pflüger; Mathew I. Ringler; Rolf B. Hilgendorf; Stephen F. Geissler; Jeffrey S. Zimmerman (IEEE J. Solid State Circuits, 2005)

A 64B CPU Pair: Dual- and Single-Processor Chips. - Erwin B. Cohen; Norman J. Rohrer; Peter A. Sandon; Miles G. Canada; Cédric Lichtenau; Mathew I. Ringler; Paul Kartschoke; Robert Floyd 002; Jan Heaslip; M. Ross; Thomas Pflueger; Rolf B. Hilgendorf; et al. (ISSCC, 2006)

Scalable and modular pervasive logic/firmware design. - Tobias Webel; Thomas Pflueger; Ralf Ludewig; Cédric Lichtenau; Walter Niklaus; Ralf Schaufler (IBM J. Res. Dev., 2012)

Beyond many-core: Commercial workload acceleration in high-end systems. - Cédric Lichtenau (ReCoSoC, 2015)

Advanced features in IBM POWER8 systems. - Balaram Sinharoy; Randal C. Swanberg; Naresh Nayar; Bruce G. Mealey; Jeffrey Stuecheli; Berni Schiefer; Jens Leenstra; Joefon Jann; P. Oehler; D. Levitan; S. Eisen; D. Sanner; et al. (IBM J. Res. Dev., 2015)

Quad Precision Floating Point on the IBM z13. - Cédric Lichtenau; Steven R. Carlough; Silvia Melitta Müller (ARITH, 2016)

SIMD Multi Format Floating-Point Unit on the IBM z15(TM). - Stefan Payer; Cédric Lichtenau; Michael Klein; Kerstin Schelm; Petra Leber; Nicol Hofmann; Tina Babinsky (ARITH, 2020)

Design of the IBM z15 microprocessor. - Anthony Saporito; Martin Recktenwald; Christian Jacobi 002; Gerrit Koch; Deanna Postles Dunn Berger; Robert J. Sonnelitter; Craig R. Walters; Jang-Soo Lee; Cédric Lichtenau; Ulrich Mayer; Eduard Herkel; Stefan Payer; et al. (IBM J. Res. Dev., 2020)

AI accelerator on IBM telum processor: industrial product. - Cédric Lichtenau; Alper Buyuktosunoglu; Ramon Bertran; Peter Figuli; Christian Jacobi 002; Nikolaos Papandreou; Haris Pozidis; Anthony Saporito; Andrew Sica; Elpida Tzortzatos (ISCA, 2022)

IBM Telum: a 16-Core 5+ GHz DCM. - Ofer Geva; Christopher J. Berry; Robert J. Sonnelitter; David Wolpert 001; Adam Collura; Thomas Strach; Di Phan; Cédric Lichtenau; Alper Buyuktosunoglu; Hubert Harrer; Jeffrey A. Zitz; Chad Marquart; et al. (ISSCC, 2022)

Acceleration of Decision-Tree Ensemble Models on the IBM Telum Processor. - Nikolaos Papandreou; Jan van Lunteren; Andreea Anghel; Thomas P. Parnell; Martin Petermann; Milos Stanisavljevic; Cédric Lichtenau; Andrew Sica; Dominic Röhm; Elpida Tzortzatos; Haralampos Pozidis (ISCAS, 2023)

The IBM Telum II Processor. - Christopher J. Berry; Michael J. Becht; Tim E. Bubb; Howard Haynie; Robert J. Sonnelitter; Katie Seggerman; Jonathan Hsieh; Edward Malley; Mike Cadigan; Susan M. Eickhoff; Matthias Klein; Craig R. Walters; et al. (IEEE Micro, 2025)