IP watermark verification based on power consumption analysis. - Cédric Marchand 002; Lilian Bossuet; Edward Jung (SoCC, 2014)

Low-level implementation and side-channel detection of stealthy hardware trojans on field programmable gate arrays. - Cédric Marchand 002; Julien Francq (IET Comput. Digit. Tech., 2014)

Identification of embedded control units by state encoding and power consumption analysis. - Edward Jung; Cédric Marchand 002; Lilian Bossuet (SAC, 2015)

Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only). - Cédric Marchand 002; Lilian Bossuet; Abdelkarim Cherkaoui (FPGA, 2016)

Design and Characterization of the TERO-PUF on SRAM FPGAs. - Cédric Marchand 002; Lilian Bossuet; Abdelkarim Cherkaoui (ISVLSI, 2016)

Identification of IP control units by state encoding and side channel verification. - Edward Jung; Lilian Bossuet; Seonho Choi; Cédric Marchand 002 (Microprocess. Microsystems, 2016)

Design, Evaluation, and Optimization of Physical Unclonable Functions Based on Transient Effect Ring Oscillators. - Abdelkarim Cherkaoui; Lilian Bossuet; Cédric Marchand 002 (IEEE Trans. Inf. Forensics Secur., 2016)

On the security evaluation of the ARM TrustZone extension in a heterogeneous SoC. - El Mehdi Benhani; Cédric Marchand 002; Alain Aubert; Lilian Bossuet (SoCC, 2017)

Area-oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti-counterfeiting schemes. - Cédric Marchand 002; Lilian Bossuet; Kris Gaj (Int. J. Circuit Theory Appl., 2017)

Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices. - Ian O'Connor; Mayeul Cantan; Cédric Marchand 002; Bertrand Vilquin; Stefan Slesazeck; Evelyn T. Breyer; Halid Mulaosmanovic; Thomas Mikolajick; Bastien Giraud; Jean-Philippe Noel; Adrian M. Ionescu; Igor Stolichnov (VLSI-SoC, 2018)

Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF. - Cédric Marchand 002; Lilian Bossuet; Ugo Mureddu; Nathalie Bochard; Abdelkarim Cherkaoui; Viktor Fischer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. - Arnaud Poittevin; Chhandak Mukherjee; Ian O'Connor; Cristell Maneux; Guilhem Larrieu; Marina Deng; Sébastien Le Beux; François Marc; Aurélie Lecestre; Cédric Marchand 002; Abhishek Kumar (VLSI-SoC (Selected Papers), 2020)

Emerging Technologies: Challenges and Opportunities for Logic Synthesis. - Alberto Bosio; Mayeul Cantan; Cédric Marchand 002; Ian O'Connor; Petr Fiser; Arnaud Poittevin; Marcello Traiola (DDECS, 2021)

FeFET based Logic-in-Memory: an overview. - Cédric Marchand 002; Ian O'Connor; Mayeul Cantan; Evelyn T. Breyer; Stefan Slesazeck; Thomas Mikolajick (DTIS, 2021)

Hardware Emulation of FeFET On FPGA. - Paul-Antoine Matrangolo; Cédric Marchand 002; David Navarro; Ian O'Connor (ISVLSI, 2022)

A Logic Cell Design and routing Methodology Specific to VNWFET. - Arnaud Poittevin; Ian O'Connor; Cédric Marchand 002; Alberto Bosio; Cristell Maneux; Chhandak Mukherjee; Guilhem Larrieu; Abhishek Kumar (NEWCAS, 2022)

EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. - Fabio Pavanello; Cédric Marchand 002; Ian O'Connor; Régis Orobtchouk; Fabien Mandorlo; Xavier Letartre; Sébastien Cueff; Elena-Ioana Vatajelu; Giorgio Di Natale; Benoit Cluzel; Aurelien Coillet; Benoît Charbonnier; et al. (ETS, 2023)

Energy-efficient Computation-In-Memory Architecture using Emerging Technologies. - Rajendra Bishnoi; Sumit Diware; Anteneh Gebregiorgis; Simon Thomann; Sara Mannaa; Bastien Deveautour; Cédric Marchand 002; Alberto Bosio; Damien Deleruyelle; Ian O'Connor; Hussam Amrouch; Said Hamdioui (ICM, 2023)

Non Volatile Operators Emulation Platform. - Alban Nicolas; Cédric Marchand 002; David Navarro (NANOARCH, 2023)

FeFET based Logic-in-Memory design methodologies, tools and open challenges. - Cédric Marchand 002; Alban Nicolas; Paul-Antoine Matrangolo; David Navarro; Alberto Bosio; Ian O'Connor (VLSI-SoC, 2023)

NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. - Fabio Pavanello; Cédric Marchand 002; Ian O'Connor; Régis Orobtchouk; Fabien Mandorlo; Xavier Letartre; Sébastien Cueff; Elena-Ioana Vatajelu; Giorgio Di Natale; Benoit Cluzel; Aurelien Coillet; Benoît Charbonnier; et al. (CoRR, 2023)

FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation. - Ian O'Connor; Sara Mannaa; Alberto Bosio; Bastien Deveautour; Damien Deleruyelle; Tetiana Obukhova; Cédric Marchand 002; Jens Trommer; Çigdem Çakirlar; Bruno Neckel Wesling; Thomas Mikolajick; Oskar Baumgartner; et al. (DATE, 2024)

Security Layers and Related Services within the Horizon Europe NEUROPULS Project. - Fabio Pavanello; Cédric Marchand 002; Paul Jiménez; Xavier Letartre; Ricardo Chaves; Niccolò Marastoni; Alberto Lovato; Mariano Ceccato; George Papadimitriou 001; Vasileios Karakostas; Dimitris Gizopoulos; Roberta Bardini; et al. (DATE, 2024)

3D VNWFET-Based Standard Cell Library Design Flow: from Circuit and Physical Design to Logic Synthesis. - Sara Mannaa; Cédric Marchand 002; Damien Deleruyelle; Bastien Deveautour; Alberto Bosio; Christoph Lenz; Oskar Baumgartner; Ian O'Connor (VLSI-SoC, 2024)

A Novel Design Technique for Enhanced Security and New Applications of Ferroelectric-Based Non-Volatile SRAM. - Lucas Rhetat; Jean-Philippe Noel; Bastien Giraud; Laurent Grenouillet; Julie Laguerre; Cédric Marchand 002; Ian O'Connor (VLSI-SoC, 2024)

Complexity Assessment of Analog Security Primitives Using the Disentropy of Autocorrelation. - Paul Jiménez; Raphael Cardoso; Mauricio Gomes de Queiroz; Mohab Abdalla; Cédric Marchand 002; Xavier Letartre; Fabio Pavanello (CoRR, 2024)