Specifying and Verifying a Decimal Representation in Java for Smart Cards. - Cees-Bart Breunesse; Bart Jacobs 001; Joachim van den Berg (AMAST, 2002)

Formal methods for smart cards: an experience report. - Cees-Bart Breunesse; Néstor Cataño; Marieke Huisman; Bart Jacobs 001 (Sci. Comput. Program., 2005)

Towards Fully Automated Analysis of Whiteboxes: Perfect Dimensionality Reduction for Perfect Leakage. - Cees-Bart Breunesse; Ilya Kizhvatov; Ruben Muijrers; Albert Spruyt (IACR Cryptol. ePrint Arch., 2018)

Verification of Power-based Side-channel Leakage through Simulation. - Yuan Yao; Patrick Schaumont; Jasper Van Woudenberg; Cees-Bart Breunesse; Edgar Mateos Santillan; Steve Stecyk (MWSCAS, 2020)

Rewrite to Reinforce: Rewriting the Binary to Apply Countermeasures against Fault Injection. - Pantea Kiaei; Cees-Bart Breunesse; Mohsen Ahmadi; Patrick Schaumont; Jasper Van Woudenberg (DAC, 2021)

Gate-Level Side-Channel Leakage Assessment with Architecture Correlation Analysis. - Pantea Kiaei; Yuan Yao; Zhenyuan Liu; Nicole Fern; Cees-Bart Breunesse; Jasper Van Woudenberg; Kate Gillis; Alex Dich; Peter Grossmann; Patrick Schaumont (CoRR, 2022)

Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance. - Sohrab Aftabjahani; Mark Tehranipoor; Farimah Farahmandi; Bulbul Ahmed; Ryan Kastner; Francesco Restuccia 002; Andres Meza 001; Kaki Ryan; Nicole Fern; Jasper Van Woudenberg; Rajesh Velegalati; Cees-Bart Breunesse; et al. (VTS, 2023)

Improving CPU Fault Injection Simulations: Insights from RTL to Instruction-Level Models. - Jasper Van Woudenberg; Rajesh Velegalati; Cees-Bart Breunesse; Dennis Vermoen Riscure (FDTC, 2024)

Gate-Level Side-Channel Leakage Ranking With Architecture Correlation Analysis. - Pantea Kiaei; Yuan Yao; Zhenyuan Liu; Nicole Fern; Cees-Bart Breunesse; Jasper Van Woudenberg; Kate Gillis; Alex Dich; Peter Grossmann; Patrick Schaumont (IEEE Trans. Emerg. Top. Comput., 2024)