Reconfigurable and Dynamically Transformable In-Cache-MPUF System With True Randomness Based on the SOT-MRAM. - Zhengyi Hou; Zhaohao Wang; Chao Wang 094; Min Wang 033; You Wang 002; Xueyan Wang; Cenlin Duan; Jianlei Yang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. - Cenlin Duan; Jianlei Yang 001; Yiou Wang; Yikun Wang; Yingjie Qi; Xiaolin He; Bonan Yan; Xueyan Wang; Xiaotao Jia; Weisheng Zhao (DAC, 2024)

DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory. - Cenlin Duan; Jianlei Yang 001; Xiaolin He; Yingjie Qi; Yikun Wang; Yiou Wang; Ziyan He; Bonan Yan; Xueyan Wang; Xiaotao Jia; Weitao Pan; Weisheng Zhao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices. - Ao Zhou; Jianlei Yang 001; Yingjie Qi; Tong Qiao; Yumeng Shi; Cenlin Duan; Weisheng Zhao; Chunming Hu (IEEE Trans. Computers, 2024)

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures. - Yingjie Qi; Jianlei Yang 001; Yiou Wang; Yikun Wang; Dayu Wang; Ling Tang; Cenlin Duan; Xiaolin He; Weisheng Zhao (CoRR, 2025)

Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity. - Cenlin Duan; Jianlei Yang 001; Yikun Wang; Yiou Wang; Yingjie Qi; Xiaolin He; Bonan Yan; Xueyan Wang; Xiaotao Jia; Weisheng Zhao (CoRR, 2025)