Introduction of Fault-Tolerance Mechanisms for Permanent Failures in Coherent Shared-Memory Many-Core Architectures. (Introduction de mécanismes de tolérance aux pannes franches dans les architectures de processeur « many-core » à mémoire partagée cohérente). - César Fuguet Tortolero (2015)

A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols. - Julie Dumas; Eric Guthmuller; César Fuguet Tortolero; Frédéric Pétrot (ARCS, 2017)

A Programmable Inbound Transfer Processor for Active Messages in Embedded Multicore Systems. - Yves Durand; Christian Bernard; Romain Lemaire; César Fuguet Tortolero; Emilie Garat (DSD, 2017)

Trace-driven exploration of sharing set management strategies for cache coherence in manycores. - Julie Dumas; Eric Guthmuller; César Fuguet Tortolero; Frédéric Pétrot (NEWCAS, 2017)

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. - Eric Guthmuller; César Fuguet Tortolero; Pascal Vivet; Christian Bernard; Ivan Miro Panades; Jean Durupt; E. Beignc; Didier Lattard; Séverine Cheramy; Alain Greiner; Quentin L. Meunier; Pirouz Bazargan-Sabet (ESSCIRC, 2018)

WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs. - Aditya Narayan; Yvain Thonnart; Pascal Vivet; César Fuguet Tortolero; Ayse K. Coskun (DATE, 2019)

POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems. - Yvain Thonnart; Stéphane Bernabé; Jean Charbonnier; Christian Bernard; David Coriat; César Fuguet Tortolero; Pierre Tissier; Benoît Charbonnier; Stéphane Malhouitre; Damien Saint-Patrice; Myriam Assous; Aditya Narayan; et al. (DATE, 2020)

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; Guillaume Moritz; Ivan Miro-Panades; César Fuguet Tortolero; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (ISSCC, 2020)

Storage Class Memory with Computing Row Buffer: A Design Space Exploration. - Valentin Egloff; Jean-Philippe Noel; Maha Kooli; Bastien Giraud; Lorenzo Ciampolini; Roman Gauchi; César Fuguet Tortolero; Eric Guthmuller; Mathieu Moreau; Jean-Michel Portal (DATE, 2021)

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; César Fuguet Tortolero; Ivan Miro-Panades; Guillaume Moritz; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (IEEE J. Solid State Circuits, 2021)

Accelerating Variants of the Conjugate Gradient with the Variable Precision Processor. - Yves Durand; Eric Guthmuller; César Fuguet Tortolero; Jérôme Fereyre; Andrea Bocco; Riccardo Alidori (ARITH, 2022)

HPDcache: Open-Source High-Performance L1 Data Cache for RISC-V Cores. - César Fuguet Tortolero (CF, 2023)

Breaking the Memory Wall with a Flexible Open-Source L1 Data-Cache. - Davy Million; Noelia Oliete-Escuín; César Fuguet (DATE, 2024)

A Variable and Extended Precision (VRP) Accelerator and its 22 nm SoC Implementation. - César Fuguet; Eric Guthmuller; Andrea Bocco; Jérôme Fereyre; Adrian Evans; Yves Durand (DCIS, 2024)

OpenSource Heterogeneous Chiplet-based Computing Architectures. - Adrian Evans; César Fuguet; Davy Million (ICCAD, 2024)

Page size exploration for RISC-V systems: the case for HPC. - Eduardo Tomasi; César Fuguet; Christian Fabre; Frédéric Pétrot (RSP, 2024)

Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation. - Eric Guthmuller; César Fuguet; Andrea Bocco; Jérôme Fereyre; Riccardo Alidori; Ihsane Tahir; Yves Durand (IEEE Trans. Computers, 2024)

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution. - Zexin Fu; Riccardo Tedeschi; Gianmarco Ottavi; Nils Wistoff; César Fuguet; Davide Rossi; Luca Benini (CF, 2025)

Hardware-Software Co-Design for Supporting Shared Distributed Virtual Memory. - Eduardo Tomasi; César Fuguet; Christian Fabre; Frédéric Pétrot (CF (Companion), 2025)

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture. - Riccardo Tedeschi; Gianmarco Ottavi; Côme Allart; Nils Wistoff; Zexin Fu; Filippo Grillotti; Fabio De Ambroggi; Elio Guidetti; Jean-Baptiste Rigaud; Olivier Potin; Jean-Roch Coulon; César Fuguet; et al. (CoRR, 2025)