Loopback architecture for wafer-level at-speed testing of embedded HyperTransportTM processor links. - Alvin Leng Sun Loke; Bruce Andrew Doyle; Michael M. Oshima; Wade L. Williams; Robert G. Lewis; Charles Lin Wang; Audie Hanpachern; Karen M. Tucker; Prashanth Gurunath; Gladney C. Asada; Chad O. Lackey; Tin Tin Wee; et al. (CICC, 2009)

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors. - Bruce Andrew Doyle; Alvin Leng Sun Loke; Sanjeev K. Maheshwari; Charles Lin Wang; Dennis Michael Fischette; Jeffrey G. Cooper; Sanjeev K. Aggarwal; Tin Tin Wee; Chad O. Lackey; Harishkumar S. Kedarnath; Michael M. Oshima; Gerry R. Talbot; et al. (A-SSCC, 2011)