Register allocation for data flow graphs with conditional branches and loops. - Chaeryung Park; Taewhan Kim 001; C. L. Liu 001 (EURO-DAC, 1993)

Register Allocation - A Hierarchical Reduction Approach. - Chaeryung Park; Taewhan Kim 001; C. L. Liu 001 (J. VLSI Signal Process., 1998)

An efficient data path synthesis algorithm for behavioral-level power optimization. - Chaeryung Park; Taewhan Park; C. L. Liu 001 (ISCAS (1), 1999)

An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization. - Chaeryung Park; Taewhan Kim 001; C. L. Liu 001 (VLSI Design, 2000)

Placement-Aware 3D Net-to-Pad Assignment for Array-Style Hybrid Bonding 3D ICs. - Pruek Vanna-Iampikul; Jun-Sik Yoon; Chaeryung Park; Gary Yeap; Sung Kyu Lim (ISPD, 2025)