Modeling and Analysis of Noise Margin in SET Logic. - Chaitanya Sathe; Santanu Mahapatra (VLSI Design, 2007)

Automated design and optimization of circuits in emerging technologies. - Rajesh Amratlal Thakker; Chaitanya Sathe; Angada B. Sachid; Maryam Shojaei Baghini; V. Ramgopal Rao; Mahesh B. Patil (ASP-DAC, 2009)

A Novel Table-Based Approach for Design of FinFET Circuits. - Rajesh Amratlal Thakker; Chaitanya Sathe; Angada B. Sachid; Maryam Shojaei Baghini; V. Ramgopal Rao; Mahesh B. Patil (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework. - Angada B. Sachid; Rajesh Amratlal Thakker; Chaitanya Sathe; Maryam Shojaei Baghini; Dinesh Kumar Sharma; V. Ramgopal Rao; Mahesh B. Patil (ISQED, 2010)

A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance. - Rajesh Amratlal Thakker; Chaitanya Sathe; Maryam Shojaei Baghini; Mahesh B. Patil (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Computational study of graphene nanopore sensor for DNA sensing - Chaitanya Sathe (2014)