Synthesis of Synchronous Sequential Logic Circuits from Partial Input/Output Sequences. - Chaiyasit Manovit; Chatchawit Aporntewan; Prabhas Chongstitvatana (ICES, 1998)

TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model. - Sudheendra Hangal; Durgam Vahia; Chaiyasit Manovit; Juin-Yeu Joseph Lu; Sridhar Narayanan (ISCA, 2004)

Efficient algorithms for verifying memory consistency. - Chaiyasit Manovit; Sudheendra Hangal (SPAA, 2005)

Testing implementations of transactional memory. - Chaiyasit Manovit; Sudheendra Hangal; Hassan Chafi; Austen McDonald; Christos Kozyrakis; Kunle Olukotun (PACT, 2006)

Completely verifying memory consistency of test program executions. - Chaiyasit Manovit; Sudheendra Hangal (HPCA, 2006)

Historical Research Using Email Archives. - Sudheendra Hangal; Vihari Piratla; Chaiyasit Manovit; Peter Chan; Glynn Edwards; Monica S. Lam (CHI Extended Abstracts, 2015)