Legalization algorithm for multiple-row height standard cell design. - Wing-Kai Chow; Chak-Wa Pui; Evangeline F. Y. Young (DAC, 2016)

RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. - Chak-Wa Pui; Gengjie Chen; Wing-Kai Chow; Ka-Chun Lam; Jian Kuang 001; Peishan Tu; Hang Zhang 010; Evangeline F. Y. Young; Bei Yu 001 (ICCAD, 2016)

Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). - Chak-Wa Pui; Gengjie Chen; Yuzhe Ma; Evangeline F. Y. Young; Bei Yu 001 (ICCAD, 2017)

A two-step search engine for large scale boolean matching under NP3 equivalence. - Chak-Wa Pui; Peishan Tu; Haocheng Li; Gengjie Chen; Evangeline F. Y. Young (ASP-DAC, 2018)

Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration. - Peishan Tu; Chak-Wa Pui; Evangeline F. Y. Young (ACM Great Lakes Symposium on VLSI, 2018)

RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs. - Gengjie Chen; Chak-Wa Pui; Wing-Kai Chow; Ka-Chun Lam; Jian Kuang 001; Evangeline F. Y. Young; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Detailed routing by sparse grid graph and minimum-area-captured path search. - Gengjie Chen; Chak-Wa Pui; Haocheng Li; Jingsong Chen; Bentian Jiang; Evangeline F. Y. Young (ASP-DAC, 2019)

Device Layer-Aware Analytical Placement for Analog Circuits. - Biying Xu; Shaolan Li; Chak-Wa Pui; Derong Liu 002; Linxiao Shen; Yibo Lin; Nan Sun 001; David Z. Pan (ISPD, 2019)

An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems. - Chak-Wa Pui; Gang Wu; Freddy Y. C. Mang; Evangeline F. Y. Young (SLIP, 2019)

CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model. - Jinwei Liu; Chak-Wa Pui; Fangzhou Wang; Evangeline F. Y. Young (DAC, 2020)

Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search. - Gengjie Chen; Chak-Wa Pui; Haocheng Li; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration. - Peishan Tu; Chak-Wa Pui; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. - Chak-Wa Pui; Evangeline F. Y. Young (ACM Trans. Design Autom. Electr. Syst., 2020)

Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment. - Dan Zheng; Xiaopeng Zhang 009; Chak-Wa Pui; Evangeline F. Y. Young (ASP-DAC, 2021)

Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration. - Xinyi Zhou 010; Junjie Ye; Chak-Wa Pui; Kun Shao; Guangliang Zhang; Bin Wang 034; Jianye Hao; Guangyong Chen; Pheng-Ann Heng (ICCAD, 2022)

TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction. - Shixiong Kai; Chak-Wa Pui; Fangzhou Wang; Shougao Jiang; Bin Wang 034; Yu Huang 005; Jianye Hao (DATE, 2023)