LAST: a Layout Area and Shape function esTimator for high level applications. - Fadi J. Kurdahi; Champaka Ramachandran (EURO-DAC, 1991)

Accurate layout area and delay modeling for system level design. - Champaka Ramachandran; Fadi J. Kurdahi; Daniel Gajski; Allen C.-H. Wu; Viraphol Chaiyakul (ICCAD, 1992)

Evaluating layout area tradeoffs for high level applications. - Fadi J. Kurdahi; Champaka Ramachandran (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Incorporating the Controller Effects During Register Transfer Level Synthesis. - Champaka Ramachandran; Fadi J. Kurdahi (EDAC-ETC-EUROASIC, 1994)

A performance driven logic synthesis system using delay estimator. - Yulin Chen; Wei Kang Tsai; Fadi J. Kurdahi; Tzong-Dar Her; Champaka Ramachandran (Great Lakes Symposium on VLSI, 1994)

An Empirical Study on the Effects of Physical Design in High-Level Synthesis. - Pradip K. Jha; Champaka Ramachandran; Nikil D. Dutt; Fadi J. Kurdahi (VLSI Design, 1994)

On the intrinsic Rent parameter and spectra-based partitioning methodologies. - Lars W. Hagen; Andrew B. Kahng; Fadi J. Kurdahi; Champaka Ramachandran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications. - Champaka Ramachandran; Fadi J. Kurdahi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)