Design and Analysis of a Low Power VLIW DSP Core. - Chan-Hao Chang; Diana Marculescu (ISVLSI, 2006)

A 250Mb/s-to-3.4Gb/s HDMI receiver with adaptive loop updating frequencies and an adaptive equalizer. - Yan-Bin Luo; Ping Chen; Qui-Ting Chen; Chih-Yong Wang; Chan-Hao Chang; Szu-Jui Fu; Chien-Ming Chen; Hung-Sung Li (ISSCC, 2009)