A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm2 Controller and 80ns Recovery Time. - Minho Choi; Chan-Ho Kye; Jonghyun Oh; Min-Seong Choo; Deog-Kyoon Jeong (ISSCC, 2019)

A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop. - Han-Gon Ko; Soyeong Shin; Chan-Ho Kye; Sang-Yoon Lee 006; Jaekwang Yun; Hae-Kang Jung; Doobock Lee; Suhwan Kim 001; Deog-Kyoon Jeong (VLSI Circuits, 2019)

A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces. - Soyeong Shin; Han-Gon Ko; Chan-Ho Kye; Sang-Yoon Lee 006; Jaekwang Yun; Doobock Lee; Hae-Kang Jung; Suhwan Kim 001; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS. - Chan-Ho Kye; Han-Gon Ko; Jinhyung Lee; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 0.000261 mm2 Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS. - Chan-Ho Kye; Kyojin Choo (A-SSCC, 2023)

A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Frequency Detector in 40-nm CMOS Technology. - Hong-Seok Choi; Jae-Geon Lee; Kwang-Ho Lee; Daehyun Koh; Jung-Woo Sull; Hyungrok Do; Chan-Ho Kye; Deog-Kyoon Jeong; Min-Seong Choo (A-SSCC, 2024)

Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC. - Chan-Ho Kye; Yu-Jin Byeon; Kyojin Choo; Min-Seong Choo (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)