64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. - Kuo-Hsing Cheng; Shun-Wen Cheng; Chan-Wei Huang (IWSOC, 2004)

Self-sampled vernier delay line for built-in clock jitter measurement. - Kuo-Hsing Cheng; Chan-Wei Huang; Shu-Yu Jiang (ISCAS, 2006)

Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System. - Shu-Yu Jiang; Chan-Wei Huang; Yu-Lung Lo; Kuo-Hsing Cheng (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)