Fairness of transitions in diagnosability analysis of hybrid systems. - Santosh Biswas; Chandan Karfa; Himani Kanwar; Dipankar Sarkar 001; Siddhartha Mukhopadhyay; Amit Patra (ACC, 2006)

A Formal Verification Method of Scheduling in High-level Synthesis. - Chandan Karfa; Chittaranjan A. Mandal; Dipankar Sarkar 001; S. R. Pentakota; Chris Reade (ISQED, 2006)

Verification of Scheduling in High-level Synthesis. - Chandan Karfa; Chittaranjan A. Mandal; Dipankar Sarkar 001; S. R. Pentakota; Chris Reade (ISVLSI, 2006)

Hand-in-hand verification of high-level synthesis. - Chandan Karfa; Dipankar Sarkar 001; Chittaranjan A. Mandal; Chris Reade (ACM Great Lakes Symposium on VLSI, 2007)

Register Sharing Verification During Data-Path Synthesis. - Chandan Karfa; Chittaranjan A. Mandal; Dipankar Sarkar 001; Chris Reade (ICCTA, 2007)

An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. - Chandan Karfa; Dipankar Sarkar 001; Chitta Mandal; P. Kumar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques. - Chandan Karfa; Dipankar Sarkar 001; Chittaranjan A. Mandal (ISVLSI, 2010)

Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. - Chandan Karfa; Dipankar Sarkar 001; Chitta Mandal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Equivalence Checking of Array-Intensive Programs. - Chandan Karfa; Kunal Banerjee 001; Dipankar Sarkar 001; Chitta Mandal (ISVLSI, 2011)

Verification of Register Transfer Level Low Power Transformations. - Chandan Karfa; Chitta Mandal; Dipankar Sarkar 001 (ISVLSI, 2011)

A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques. - Kunal Banerjee 001; Chandan Karfa; Dipankar Sarkar 001; Chittaranjan Mandal 001 (ISED, 2012)

Formal verification of code motion techniques using data-flow-driven equivalence checking. - Chandan Karfa; Chittaranjan A. Mandal; Dipankar Sarkar 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

Verification of KPN Level Transformations. - Chandan Karfa; Dipankar Sarkar 001; Chittaranjan A. Mandal (VLSI Design, 2013)

Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors. - Chandan Karfa; Kunal Banerjee 001; Dipankar Sarkar 001; Chittaranjan A. Mandal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Verification of Code Motion Techniques Using Value Propagation. - Kunal Banerjee 001; Chandan Karfa; Dipankar Sarkar 001; Chittaranjan A. Mandal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Translation Validation of Loop Invariant Code Optimizations Involving False Computations. - Ramanuj Chouksey; Chandan Karfa; Purandar Bhaduri (VDAT, 2017)

xMAS Based Accurate Modeling and Progress Verification of NoCs. - Surajit Das; Chandan Karfa; Santosh Biswas (VDAT, 2017)

Automatic detection of inverse operations while avoiding loop unrolling. - Kunal Banerjee 001; Ramanuj Chouksey; Chandan Karfa; Pankaj Kumar Kalita (ICSE (Companion Volume), 2018)

Compiler-agnostic Translation Validation. - Kunal Banerjee 001; Chandan Karfa (ISEC, 2018)

Formal Verification of Optimizing Transformations during High-level Synthesis. - Ramanuj Chouksey; Chandan Karfa; Purandar Bhaduri (ISEC, 2019)

User Guided Register Manipulation in Digital Circuits. - Priyanka Panigrahi; Rajesh Kumar Jha; Chandan Karfa (VDAT, 2019)

Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples. - Ramanuj Chouksey; Chandan Karfa; Purandar Bhaduri (VLSID, 2019)

A Quick Introduction to Functional Verification of Array-Intensive Programs. - Kunal Banerjee 001; Chandan Karfa (CoRR, 2019)

Verification of parallelising transformations of KPN models. - Chandan Karfa; Dipankar Sarkar 001; Chittaranjan Mandal 001 (IET Cyper-Phys. Syst.: Theory & Appl., 2019)

Counter-example generation procedure for path-based equivalence checkers. - Ramanuj Chouksey; Chandan Karfa; Kunal Banerjee 001; Pankaj Kumar Kalita; Purandar Bhaduri (IET Softw., 2019)

Translation Validation of Code Motion Transformations Involving Loops. - Ramanuj Chouksey; Chandan Karfa; Purandar Bhaduri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

SAT Based Partial Attack on Compound Logic Locking. - Melbin John; Aadil Hoda; Ramanuj Chouksey; Chandan Karfa (AsianHOST, 2020)

Is Register Transfer Level Locking Secure? - Chandan Karfa; Ramanuj Chouksey; Christian Pilato; Siddharth Garg; Ramesh Karri (DATE, 2020)

Automatic Inverse Operation Detection and its Impact in High-level Synthesis. - Pankaj Kumar Kalita; Ramanuj Chouksey; Chandan Karfa (VDAT, 2020)

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. - Benjamin Tan 001; Ramesh Karri; Nimisha Limaye; Abhrajit Sengupta; Ozgur Sinanoglu; Md. Moshiur Rahman 001; Swarup Bhunia; Danielle Duvalsaint; Ronald D. Blanton; Amin Rezaei 001; Yuanqi Shen; Hai Zhou 001; et al. (CoRR, 2020)

Verification of Scheduling of Conditional Behaviors in High-Level Synthesis. - Ramanuj Chouksey; Chandan Karfa (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock. - Surajit Das; Chandan Karfa; Santosh Biswas (IEEE Trans. Very Large Scale Integr. Syst., 2020)

HOST: HLS Obfuscations against SMT ATtack. - Chandan Karfa; T. M. Abdul Khader; Yom Nigam; Ramanuj Chouksey; Ramesh Karri (DATE, 2021)

Reverse Engineering Register to Variable Mapping in High-level Synthesis. - Mohammed Abderehman; Rupak Gupta; Chandan Karfa (ISVLSI, 2021)

VP_TT: A value propagation based equivalence checker for testability transformations. - Ramanuj Chouksey; Sachin Kumar Maddheshiya; Chandan Karfa (IET Softw., 2021)

HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems. - Debabrata Senapati; Arnab Sarkar 001; Chandan Karfa (ACM Trans. Embed. Comput. Syst., 2021)

ImageSpec: Efficient High-Level Synthesis of Image Processing Applications. - Abdul Khader Thalakkattu Moosa; Nilotpola Sarma; Chandan Karfa (DSD, 2022)

GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking. - Gagan Gayari; Chandan Karfa; Prithwijit Guha (ACM Great Lakes Symposium on VLSI, 2022)

Performance-Effective DAG Scheduling for Heterogeneous Distributed Systems. - Debabrata Senapati; Arnab Sarkar 001; Chandan Karfa (ICDCN, 2022)

DEEQ: Data-driven End-to-End EQuivalence Checking of High-level Synthesis. - Mohammed Abderehman; Theegala Rakesh Reddy; Chandan Karfa (ISQED, 2022)

Corruption Exposes You: Statistical Key Recovery from Compound Logic Locking. - Arshdeep Kaur; Sayandeep Saha; Chandan Karfa; Debdeep Mukhopadhyay (ISQED, 2022)

Accelerating NoC Verification Using a Complete Model and Active Window. - Surajit Das; Chandan Karfa; Santosh Biswas (IEEE Access, 2022)

Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC. - Surajit Das; Chandan Karfa (IEEE Embed. Syst. Lett., 2022)

Secure Register Allocation for Trusted Code Generation. - Priyanka Panigrahi; Vemuri Sahithya; Chandan Karfa; Prabhat Mishra 001 (IEEE Embed. Syst. Lett., 2022)

PRESTO: A Penalty-Aware Real-Time Scheduler for Task Graphs on Heterogeneous Platforms. - Debabrata Senapati; Arnab Sarkar 001; Chandan Karfa (IEEE Trans. Computers, 2022)

BLAST: Belling the Black-Hat High-Level Synthesis Tool. - Mohammed Abderehman; Rupak Gupta; Theegala Rakesh Reddy; Chandan Karfa (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

FastSim: A Fast Simulation Framework for High-Level Synthesis. - Mohammed Abderehman; Jayprakash Patidar; Jay H. Oza; Yom Nigam; T. M. Abdul Khader; Chandan Karfa (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Quantifying Information Leakage for Security Verification of Compiler Optimizations. - Priyanka Panigrahi; Abhik Paul; Chandan Karfa (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

An Investigation into the Security of Register Allocation with Spilling and Splitting. - Priyanka Panigrahi; Chandan Karfa (ISVLSI, 2023)

Energy-Aware Real-Time Scheduling of Multiple Periodic DAGs on Heterogeneous Systems. - Debabrata Senapati; Arnab Sarkar 001; Chandan Karfa (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Translation Validation of Information Leakage of Compiler Optimizations. - Priyanka Panigrahi; Chandan Karfa (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems. - Debabrata Senapati; Kousik Rajesh; Chandan Karfa; Arnab Sarkar 001 (ACM Trans. Design Autom. Electr. Syst., 2023)

LLM vs HLS for RTL Code Generation: Friend or Foe? - Sutirtha Bhattacharyya; Sutharshanan B. G; Chandan Karfa (ATS, 2024)

Security Concerns of Machine Learning Hardware. - Nilotpola Sarma; E. Bhawani Eswar Reddy; Chandan Karfa (ATS, 2024)

LEAP: Learning guided Quality Cut selection for faster Technology Mapping. - Chandrabhusan Reddy Chigarapally; Harshwardhan Nitin Bhakkad; Animesh Basak Chowdhury; Chandan Karfa; Sukanta Bhattacharjee (ICCAD, 2024)

RTL Simulation Acceleration with Machine Learning Models. - Surajit Das; Hetang Patel; Chandan Karfa; Kartheek Bellamkonda; Rahul Reddy; Disha Puri; Anshul Jain; Arijit Sur; Pradip Prajapati (ISQED, 2024)

ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation. - Bhabesh Mali; Karthik Maddala; Vatsal Gupta; Sweeya Reddy; Chandan Karfa; Ramesh Karri (ISVLSI, 2024)

NoBALL: A Novel BDD-based Attack against Logic Locking. - Praveen Karmakar; Anmoldeep Singh; Kartik Sharma; Chandan Karfa; Sukanta Bhattacharjee (ITC-Asia, 2024)

Evaluating the Robustness of Large scale eFPGA-based Hardware Redaction. - Praveen Karmakar; Marpina Bharani; Chandan Karfa (VLSID, 2024)

SRIL: Securing Registers from Information Leakage at Register Transfer Level. - Priyanka Panigrahi; Vignesh Ravichandra Rao; Thockchom Birjit Singha; Chandan Karfa (VLSID, 2024)

ERS: Energy-efficient Real-time DAG Scheduling on Uniform Multiprocessor Embedded Systems. - Debabrata Senapati; Dharmendra Maurya; Arnab Sarkar 001; Chandan Karfa (VLSID, 2024)

LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verification. - Karthik Maddala; Bhabesh Mali; Chandan Karfa (CoRR, 2024)

MaskedHLS: Domain-Specific High-Level Synthesis of Masked Cryptographic Designs. - Nilotpola Sarma; Anuj Singh Thakur; Chandan Karfa (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

LAMA: A Latency Minimum Resource Constraint Accelerator for CNN Models. - Sutirtha Bhattacharyya; Fedrick Nongpoh; Karthik Maddala; E. Bhawani Eswar Reddy; Chandan Karfa (VLSID, 2025)

TRANSPOSE: Circuit Transformations for Power Side-Channel Security at Register Transfer Level. - Nilotpola Sarma; Anuj Singh Thakur; Chandan Karfa (VLSID, 2025)

SHIELD: Security-Aware Scheduling for Real-Time DAGs on Heterogeneous Systems. - Debabrata Senapati; Pooja Bhagat; Chandan Karfa; Arnab Sarkar 001 (ACM Trans. Cyber Phys. Syst., 2025)

SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine. - Adarsh Gupta; Bhabesh Mali; Chandan Karfa (CoRR, 2025)