A Novel Methodology for Design of Cyclic Combinational Circuits. - Vinay Kumar; Chandan Kumar Jha 001; Gaurav Thapa; Anup Dandapat (J. Low Power Electron., 2016)

A Fiber Bragg Grating Strain Sensor-Based Glove to Accurately Measure the Bend Angle of the Finger Flexed at the Proximal Interphalangeal Joints. - Chandan Kumar Jha 001; Arup Lal Chakraborty (IEEE SENSORS, 2018)

Should We Code Differently When Using Approximate Circuits? - Ankita Nandi; Chandan Kumar Jha 001; Joycee Mekie (APCCAS, 2019)

SEDA - Single Exact Dual Approximate Adders for Approximate Processors. - Chandan Kumar Jha 001; Joycee Mekie (DAC, 2019)

Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs. - Chandan Kumar Jha 001; Joycee Mekie (DSD, 2019)

Quality Tunable Approximate Adder for Low Energy Image Processing Applications. - Chandan Kumar Jha 001; Ankita Nandi; Joycee Mekie (ICECS, 2019)

FPAD: A Multistage Approximation Methodology for Designing Floating Point Approximate Dividers. - Chandan Kumar Jha 001; Kailash Prasad; Vibhor Kumar Srivastava; Joycee Mekie (ISCAS, 2020)

SEDAAF: FPGA Based Single Exact Dual Approximate Adders for Approximate Processors. - Chandan Kumar Jha 001; Kailash Prasad; Arun Singh Tomar; Joycee Mekie (ISCAS, 2020)

Tunable Inexact Subtracters for Division in Image Processing Applications. - Ankita Nandi; Chandan Kumar Jha 001; Joycee Mekie (MWSCAS, 2020)

Energy and Error Analysis Framework for Approximate Computing in Mobile Applications. - Chandan Kumar Jha 001; Sneha N. Ved; Ishant Anand; Joycee Mekie (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

FPCAM: Floating Point Configurable Approximate Multiplier for Error Resilient Applications. - Chandan Kumar Jha 001; Sumit Walia; Gagan Kanojia; Joycee Mekie (ISCAS, 2021)

Zero Aware Configurable Data Encoding by Skipping Transfer for Error Resilient Applications. - Chandan Kumar Jha 001; Shreyas Singh; Riddhi Thakker; Manu Awasthi; Joycee Mekie (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Analysis of Worst-Case Data Dependent Temporal Approximation in Floating Point Units. - Chandan Kumar Jha 001; Ishita Doshi; Joycee Mekie (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Data-Aware Cache Management for Graph Analytics. - Neelam Sharma; Varun Venkitaraman; Newton; Vikash Kumar; Shubham Singhania; Chandan Kumar Jha 001 (DATE, 2022)

A fibre Bragg grating sensor-based instrumented glove for virtual rehabilitation applications. - Chandan Kumar Jha 001; Arup Lal Chakraborty (OFC, 2022)

CAR: Community Aware Graph Reordering for Efficient Cache Utilization in Graph Analytics. - Shubham Singhania; Neelam Sharma; Varun Venkitaraman; Chandan Kumar Jha 001 (VDAT, 2022)

Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound. - Anishetti Venkatesh; Chandan Kumar Jha 001; G. U. Vinod; Masahiro Fujita; Virendra Singh (VDAT, 2022)

A Fresh Perspective on DNN Accelerators by Performing Holistic Analysis Across Paradigms. - Tom Glint; Chandan Kumar Jha 001; Manu Awasthi; Joycee Mekie (CoRR, 2022)

Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core. - Sajjad Parvin; Sallar Ahmadi-Pour; Chandan Kumar Jha 001; Frank Sill Torres; Rolf Drechsler (COINS, 2023)

Analysis of Quantization Across DNN Accelerator Architecture Paradigms. - Tom Glint; Chandan Kumar Jha 001; Manu Awasthi; Joycee Mekie (DATE, 2023)

Analysis of Conventional, Near-Memory, and In-Memory DNN Accelerators. - Tom Glint; Chandan Kumar Jha 001; Manu Awasthi; Joycee Mekie (ISPASS, 2023)

Benchmarking Multiplier Architectures for MAGIC Based In-Memory Computing. - Chandan Kumar Jha 001; Rolf Drechsler (NEWCAS, 2023)

Finite State Automata Design using 1T1R ReRAM Crossbar. - Simranjeet Singh; Omar Ghazal; Chandan Kumar Jha 001; Vikas Rana; Rolf Drechsler; Rishad A. Shafik; Alex Yakovlev; Sachin B. Patkar; Farhad Merchant (NEWCAS, 2023)

Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders. - Chandan Kumar Jha 001; Ankita Nandi; Joycee Mekie (IEEE Trans. Very Large Scale Integr. Syst., 2023)

MARADIV: Library of MAGIC-Based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors. - Chandan Kumar Jha 001; Sallar Ahmadi-Pour; Rolf Drechsler (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. - Simranjeet Singh; Chandan Kumar Jha 001; Ankit Bende; Phrangboklang Lyngton Thangkhiew; Vikas Rana; Sachin B. Patkar; Rolf Drechsler; Farhad Merchant (IEEE Embed. Syst. Lett., 2023)

MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. - Simranjeet Singh; Chandan Kumar Jha 001; Ankit Bende; Vikas Rana; Sachin B. Patkar; Rolf Drechsler; Farhad Merchant (ASPDAC, 2024)

LLMs for Hardware Verification: Frameworks, Techniques, and Future Directions. - Khushboo Qayyum; Sallar Ahmadi-Pour; Chandan Kumar Jha 001; Muhammad Hassan 002; Rolf Drechsler (ATS, 2024)

Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification. - Khushboo Qayyum; Muhammad Hassan 002; Sallar Ahmadi-Pour; Chandan Kumar Jha 001; Rolf Drechsler (DAC, 2024)

LLM-Guided Formal Verification Coupled with Mutation Testing. - Muhammad Hassan 002; Sallar Ahmadi-Pour; Khushboo Qayyum; Chandan Kumar Jha 001; Rolf Drechsler (DATE, 2024)

Hidden Cost of Circuit Design with RFETs. - Sajjad Parvin; Chandan Kumar Jha 001; Frank Sill Torres; Rolf Drechsler (DATE, 2024)

Polynomial Formal Verification of Approximate Adders with Constant Cutwidth. - Mohamed A. Nadeem; Chandan Kumar Jha 001; Rolf Drechsler (ETS, 2024)

In-Memory Mirroring: Cloning Without Reading. - Simranjeet Singh; Ankit Bende; Chandan Kumar Jha 001; Vikas Rana; Rolf Drechsler; Sachin B. Patkar; Farhad Merchant (VLSI-SoC, 2024)

Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. - Ankit Bende; Simranjeet Singh; Chandan Kumar Jha 001; Tim Kempen; Felix Cüppers; Christopher Bengel; Andre Zambanini; Dennis Nielinger; Sachin B. Patkar; Rolf Drechsler; Rainer Waser; Farhad Merchant; et al. (VLSID, 2024)

Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic. - Chandan Kumar Jha 001; Sallar Ahmadi-Pour; Rolf Drechsler (VLSID, 2024)

EnR: extend and reduce methodology to enable formal verification of truncated adders. - Chandan Kumar Jha 001; Khushboo Qayyum; Muhammad Hassan 001; Rolf Drechsler (it Inf. Technol., 2024)

Lower the RISC: Designing optical-probing-attack-resistant cores. - Sajjad Parvin; Sallar Ahmadi-Pour; Chandan Kumar Jha 001; Frank Sill Torres; Rolf Drechsler (Microprocess. Microsystems, 2024)

cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits. - Chandan Kumar Jha 001; Muhammad Hassan 002; Rolf Drechsler (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing. - Chandan Kumar Jha 001; Khushboo Qayyum; Kemal Çaglar Coskun; Simranjeet Singh; Muhammad Hassan 002; Rainer Leupers; Farhad Merchant; Rolf Drechsler (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Prompt. Verify. Repeat. LLMs in the Hardware Verification Cycle. - Muhammad Hassan 002; Mohamed A. Nadeem; Khushboo Qayyum; Chandan Kumar Jha 001; Rolf Drechsler (COINS, 2025)

Polynomial Formal Verification of Sequential Circuits Using Weighted-AIGs. - Mohamed A. Nadeem; Chandan Kumar Jha 001; Rolf Drechsler (DATE, 2025)

River: Sneak Path Aware READ-based In-Memory Computing for 1T1M Memristive Crossbars. - Till Schnittka; Chandan Kumar Jha 001; Sallar Ahmadi-Pour; Rolf Drechsler (DDECS, 2025)

Large Language Models (LLMs) for Verification, Testing, and Design. - Chandan Kumar Jha 001; Muhammad Hassan 001; Khushboo Qayyum; Sallar Ahmadi-Pour; Kangwei Xu; Ruidi Qiu; Jason Blocklove; Luca Collini; Andre Nakkab; Ulf Schlichtmann; Grace Li Zhang; Ramesh Karri; et al. (ETS, 2025)

Formal Verification of Error Bounds for Resistive-Switching-Based Multilevel Matrix-Vector Multipliers. - Kemal Çaglar Coskun; Chandan Kumar Jha 001; Muhammad Hassan 002; Rolf Drechsler (ISQED, 2025)

FARAD: Automated Formal Verification of Approximate Restoring Array Dividers. - Chandan Kumar Jha 001; Khushboo Qayyum; Muhammad Hassan 001; Rolf Drechsler (VLSID, 2025)

True-PolyTronik: Securing Circuits Against Laser Logic State Imaging Attack Using RFET. - Sajjad Parvin; Chandan Kumar Jha 001; Frank Sill Torres; Rolf Drechsler (VLSID, 2025)

Polynomial Formal Verification of Multi-Valued Approximate Circuits Within Constant Cutwidth. - Mohamed A. Nadeem; Chandan Kumar Jha 001; Rolf Drechsler (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Correct and Verify - CAV: Exploiting Binary Decision Diagrams to Enable Formal Verification of Approximate Adders With Correct Carry Bits. - Chandan Kumar Jha 001; Khushboo Qayyum; Muhammad Hassan 002; Rolf Drechsler (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits. - Sallar Ahmadi-Pour; Sajjad Parvin; Chandan Kumar Jha 001; Rolf Drechsler (ACM Trans. Design Autom. Electr. Syst., 2025)