An ASIC for High Performance Stepper Motor Control. - K. V. S. H. Rao; A. Kansal; Chandra Shekhar 001; M. Srinivas; V. N. S. N. Rao (VLSI Design, 1992)

Using Dedicated Functional Simulator for ASIC Design in Indian Context. - K. V. S. H. Rao; Raj Singh; Chandra Shekhar 001 (VLSI Design, 1992)

Design of an Efficient ASIC for the Control of Microwave Ovens. - Chandra Shekhar 001; A. S. Mandal (VLSI Design, 1992)

Evolution of Architectural Concepts and Design Methods of Microprocessors. - S. Srivastava; S. C. Bose; B. P. Mathur; Arti Noor; Raj Singh; A. S. Mandal; K. Prabhakaran; Arindam Karmakar; Chandra Shekhar 001; Sudhir Kumar; Amit K. Agarwal (VLSI Design, 1998)

High Frequency Behaviour Of Electron Transport In Silicon And Its Implication For Drain Conductance Of Mos Transistors. - B. Prasad; P. J. George; Chandra Shekhar 001 (VLSI Design, 2001)

Design of an Application Specific Instruction Set Processor for Parametric Speech Synthesis. - Ravi Saini; Pramod Tanwar; A. S. Mandal; S. C. Bose; Raj Singh; Chandra Shekhar 001 (VLSI Design, 2004)

Application Specific Instruction Set Processors: Redefining Hardware-Software Boundary. - Chandra Shekhar 001; Raj Singh; A. S. Mandal; S. C. Bose; Ravi Saini; Pramod Tanwar (VLSI Design, 2004)

Evaluation of Device Parameters of HfO2/SiO2/Si Gate Dielectric Stack for MOSFETs. - A. Madan; S. C. Bose; P. J. George; Chandra Shekhar 001 (VLSI Design, 2005)

A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic. - Subhendu Kumar Sahoo; Abhijit Ashati; Rasmita Sahoo; Chandra Shekhar 001 (ICETET, 2008)

Figure-of-Merit-Based Area-Constrained Design of Differential Amplifiers. - Alpana Agarwal; Chandra Shekhar 001 (VLSI Design, 2008)

Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load. - Abhijit R. Asati; Subhendu Kumar Sahoo; Chandra Shekhar 001 (ICETET, 2009)

Dual channel addition based FFT processor architecture for signal and image processing. - Subhendu Kumar Sahoo; Chandra Shekhar 001; Sudeepti Kodali; Abhijit R. Asati; Anu Gupta (Int. J. High Perform. Syst. Archit., 2009)

Moving Object Tracking Using Object Segmentation. - Sanjay Singh 001; Srinivasa Murali Dunga; Atanendu S. Mandal; Chandra Shekhar 001; Anil Vohra (ICT, 2010)

A Novel Redundant Binary Number to Natural Binary Number Converter. - Subhendu Kumar Sahoo; Anu Gupta; Abhijit R. Asati; Chandra Shekhar 001 (J. Signal Process. Syst., 2010)

Synthesis of Analog IC Building Blocks. - Alpana Agarwal; Chandra Shekhar 001 (ISVLSI, 2011)

Automatic real-time extraction of focused regions in a live video stream using edge width information. - Sanjay Singh 001; Sumeet Saurav; Ravi Saini; Anil K. Saini; Chandra Shekhar 001; Anil Vohra (VDAT, 2014)

FPGA-based real-time object tracker using modified particle filtering and SAD computation. - Sanjay Singh 001; Ravi Saini; Sumeet Saurav; Anil K. Saini; Chandra Shekhar 001; Anil Vohra (VDAT, 2014)

A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm. - Jai Gopal Pandey; Arindam Karmakar; Chandra Shekhar 001; S. Gurunarayanan 001 (VLSID, 2014)

An embedded framework for accurate object localization using center of gravity measure with mean shift procedure. - Jai Gopal Pandey; Arindam Karmakar; Chandra Shekhar 001; S. Gurunarayanan 001 (VDAT, 2015)

An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications. - Jai Gopal Pandey; Arindam Karmakar; Chandra Shekhar 001; S. Gurunarayanan 001 (VLSID, 2015)

Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform. - Sanjay Singh 001; Atanendu Sekhar Mandal; Chandra Shekhar 001; Anil Vohra (J. Imaging, 2017)

Real-Time FPGA-Based Object Tracker with Automatic Pan-Tilt Features for Smart Video Surveillance Systems. - Sanjay Singh 001; Chandra Shekhar 001; Anil Vohra (J. Imaging, 2017)

A New XOR-FREE Approach to Implement Walsh Sequences. - Gaurav Purohit; Divya Vyas; Vinod Kumar Chaubey; Kota Solomon Raju; Chandra Shekhar 001 (Wirel. Pers. Commun., 2019)

High-Level synthesis assisted design and verification framework for automotive radar processors. - Prateek Sikka; Abhijit R. Asati; Chandra Shekhar 001 (Microprocess. Microsystems, 2020)

Speed optimal FPGA implementation of the encryption algorithms for telecom applications. - Prateek Sikka; Abhijit R. Asati; Chandra Shekhar 001 (Microprocess. Microsystems, 2020)

High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications. - Prateek Sikka; Abhijit R. Asati; Chandra Shekhar 001 (Comput. Intell., 2021)

Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications. - Prateek Sikka; Abhijit R. Asati; Chandra Shekhar 001 (Circuits Syst. Signal Process., 2021)

Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm. - Prateek Sikka; Abhijit R. Asati; Chandra Shekhar 001 (Microprocess. Microsystems, 2021)

Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis. - Prateek Sikka; Abhijit R. Asati; Chandra Shekhar 001 (Wirel. Pers. Commun., 2022)

A Three-Stage Dynamic Comparator for SAR ADC Optimized for Reduced Kickback Noise and Ultra-Low Delay. - Buddhi Prakash Sharma; Rajeev Rajagopal; Ranjeeth Sekhar; Anu Gupta; Chandra Shekhar 001 (J. Circuits Syst. Comput., 2025)