Design and Analysis of Current Starved VCO Targeting SCL 180 nm CMOS Process. - Chandra Shekhar 006; Shafi Qureshi (iSES, 2018)

Design of 50 MHz PLL using indigenous SCL 180 nm CMOS Technology. - Chandra Shekhar 006; Shafi Qureshi (iSES, 2021)