On Modeling Cross-Talk Faults. - Sujit T. Zachariah; Yi-Shing Chang; Sandip Kundu; Chandra Tirumurti (DATE, 2003)

A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. - Chandra Tirumurti; Sandip Kundu; Susmita Sur-Kolay; Yi-Shing Chang (DATE, 2004)

On modeling crosstalk faults. - Sandip Kundu; Sujit T. Zachariah; Yi-Shing Chang; Chandra Tirumurti (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Estimating Error Propagation Probabilities with Bounded Variances. - Hossein Asadi 001; Mehdi Baradaran Tahoori; Chandra Tirumurti (DFT, 2007)

Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller. - Michail Maniatakos; Naghmeh Karimi; Yiorgos Makris; Abhijit Jas; Chandra Tirumurti (DFT, 2008)

Impact analysis of performance faults in modern microprocessors. - Naghmeh Karimi; Michail Maniatakos; Chandra Tirumurti; Abhijit Jas; Yiorgos Makris (ICCD, 2009)

RT-Level Deviation-Based Grading of Functional Test Sequences. - Hongxia Fang; Krishnendu Chakrabarty; Abhijit Jas; Srinivas Patil; Chandra Tirumurti (VTS, 2009)

Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller. - Michail Maniatakos; Naghmeh Karimi; Chandra Tirumurti; Abhijit Jas; Yiorgos Makris (VTS, 2009)

Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. - Daniele Rossi 001; Martin Omaña 001; Gianluca Berghella; Cecilia Metra; Abhijit Jas; Chandra Tirumurti; Rajesh Galivanche (Conf. Computing Frontiers, 2010)

AVF Analysis Acceleration via Hierarchical Fault Pruning. - Michail Maniatakos; Chandra Tirumurti; Abhijit Jas; Yiorgos Makris (ETS, 2011)

Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor. - Naghmeh Karimi; Michail Maniatakos; Abhijit Jas; Chandra Tirumurti; Yiorgos Makris (IEEE Trans. Computers, 2011)

Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller. - Michail Maniatakos; Naghmeh Karimi; Chandra Tirumurti; Abhijit Jas; Yiorgos Makris (IEEE Trans. Computers, 2011)

Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors. - Michail Maniatakos; Chandrasekharan Tirumurti; Rajesh Galivanche; Yiorgos Makris (IEEE Trans. Computers, 2012)

Functional Test-Sequence Grading at Register-Transfer Level. - Hongxia Fang; Krishnendu Chakrabarty; Abhijit Jas; Srinivas Patil; Chandra Tirumurti (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Novel approach to reduce power droop during scan-based logic BIST. - Martin Omaña 001; Daniele Rossi 001; Filippo Fuzzi; Cecilia Metra; Chandra Tirumurti; R. Galivache (ETS, 2013)

On the Impact of Performance Faults in Modern Microprocessors. - Naghmeh Karimi; Michail Maniatakos; Chandrasekharan Tirumurti; Yiorgos Makris (J. Electron. Test., 2013)

Power droop reduction during Launch-On-Shift scan-based logic BIST. - Martin Omaña 001; Daniele Rossi 001; Edda Beniamino; Cecilia Metra; Chandra Tirumurti; Rajesh Galivanche (DFT, 2014)

Revisiting Vulnerability Analysis in Modern Microprocessors. - Michail Maniatakos; Maria K. Michael; Chandra Tirumurti; Yiorgos Makris (IEEE Trans. Computers, 2015)

Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST. - Martin Omaña 001; Daniele Rossi 001; Edda Beniamino; Cecilia Metra; Chandrasekharan Tirumurti; Rajesh Galivanche (IEEE Trans. Computers, 2016)

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. - Martin Omaña 001; Daniele Rossi 001; Filippo Fuzzi; Cecilia Metra; Chandra Tirumurti; Rajesh Galivanche (IEEE Trans. Very Large Scale Integr. Syst., 2017)